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European Physical Journal Plus (21905444)140(8)
Researchers and designers should face the challenges caused by memory and energy limitations. Quantum-dot Cellular Automata (QCA) offers a promising alternative with its high speed and low power consumption for dense emerging nano-electronic structures. Applying the approximate computing paradigm, where lower hardware complexity is prioritized over complete accuracy, can reduce power consumption. Integrating approximate computing with QCA reduces energy consumption and enhances system performance, although at the potential cost of reduced accuracy. The arithmetic unit is responsible for binary addition, subtraction, and multiplication. This article proposes a methodology for integrating QCA-based gates with approximate computing to achieve high-speed computation while minimizing resource usage. Additionally, it introduces a novel high-speed and cost-efficient design for a QCA-based approximate full adder, demonstrating improved hardware evaluation metrics, including delay, energy consumption, and acceptable error margins. The cost analysis indicates that the proposed design effectively balances circuit design trade-offs, particularly regarding delay and area. The functionality validation of the proposed circuit is assessed by the QCADesigner-E tool. Compared to the state of the art, the proposed design enhances performance metrics, achieving average improvements of 50% in delay, 26% in the number of QCA cells, and 78% in cost. These advancements are significant for the development of efficient and cost-effective QCA-based systems. Various error evaluation metrics assess the proposed approximate full adder's computational accuracy across three implementation scenarios of the 8-bit approximate adder architecture. Application-level simulation outputs show that the proposed circuits perform well in all scenarios, with the Peak-Signal-to-Noise Ratio (PSNR) exceeding 30 dB. © The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2025.
Progress in Additive Manufacturing (23639520)
Cellular structures can reduce the stiffness of Ti-6Al-4 V and prevent the stress shielding effect. This research aimed to design and mechanically characterize triply periodic minimal surface (TPMS) cellular structures for use in intervertebral lumbar cages. To identify the appropriate structure and porosity, sheet-based gyroid, diamond, and Schwarz lattice structures were designed with different porosity levels from 45 to 80% and pore size of 720 µm. The behavior of porous samples was simulated under uniaxial compression using finite element simulation to predict the elastic modulus. The structures were also built using the metal additive manufacturing method, and then their elastic modulus was obtained by the uniaxial compression test. The simulation results and experimental tests differed by less than 10%, which was acceptable. The results indicated that the gyroid and diamond structures with 70 and 75% porosity had an elastic modulus (about 9 to 16 GPa) close to the elastic modulus of bone (7 to 20 GPa). Also, due to the high surface-to-volume ratio (about 7 to 16), these cellular structures were used in the cage design. Furthermore, the behavior of designed cages was also simulated in compression, compression-shear, and torsion. The simulation results indicated that the stress field created in the cellular structure of cages was much lower than the yield strength of the material. Therefore, the study concluded that the designed cages prevented the stress shielding effect and showed an acceptable mechanical behavior. © The Author(s), under exclusive licence to Springer Nature Switzerland AG 2025.
Journal of Supercomputing (15730484)81(3)
Decimal computations have attracted a lot of attentions in computer science in recent years due to the increasing significance of decimal-based financial and commercial applications. Addition, a fundamental arithmetic operator, is crucial for performing more complex functions like multiplication and division. Thus, designing an efficient decimal addition method is essential for improving the overall performance of decimal systems. In response, this paper introduces a new hybrid decimal adder. The proposed adder integrates the Carry Skip adder with the Carry Select adder to improve delay, power consumption and area metrics. Simulations and comparisons with recent state-of-the-art Binary Coded Decimal adders highlight the advantages of our design in terms of Power-Delay Product (PDP) and Area-Delay Product (ADP). The proposed adder achieves a 62.25% reduction in PDP and a 48% reduction in ADP. Experiments and simulations were carried out using VHDL and ModelSim SE 10.6f on 90 nm CMOS technology. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.
Results in Engineering (25901230)25
Computation-in-memory (CIM) is a promising technique for overcoming the Von-Neumann bottleneck. Applying memristors in CIM reduces data transfer between processor and memory. Memristive CIM reduces energy consumption and processing time of data-intensive applications. Multipliers are one of the arithmetic circuits that play a significant role in data-intensive processing applications. Serial Material Implication (IMPLY) logic design implements arithmetic circuits by applying emerging memristive technology that enables CIM Array (CIM-A). The computational complexity of IMPLY-based multipliers for use in the CIM-A architecture is a significant design challenge. Implementing IMPLY-based crossbar array-friendly multipliers and reducing their computational cycles and energy consumption are designers' goals in applying computational applications such as convolution in the basic CIM-A architecture. This work presents unsigned and signed array multipliers using serial IMPLY logic. The proposed multipliers have improved significantly compared to State-Of-the Art (SOA) by applying the proposed Partial Product Units (PPUs) and overlapping computational steps. The number of computational steps, energy consumption, and required memristors of the proposed 8-bit unsigned array multiplier are improved by up to 36 %, 31 %, and 47 % compared to the classic designs. The proposed 8-bit signed multiplier has also improved the computational steps, energy consumption, and required memristors by up to 59 %, 54 %, and 45 %. The performance of the proposed multipliers in the applications of Gaussian blur and edge detection is also investigated, and the simulation results have shown an improvement of 31 % in energy consumption and 33 % in the number of computational steps in these applications. © 2025 The Author(s)
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively. © 2024 IEEE.
IEEE Transactions on Biomedical Circuits and Systems (19324545)18(3)pp. 478-497
In the last few decades, DNA-based self-assembly tiles has become a hot field in research due to its special applications and advantages. The regularity and strong design methods comprise other DNA-based digital circuit design methods. In addition to the obvious advantages of this method, there are challenges in performing computations based on self-assembly tiles, which have hindered the development and construction of large computing circuits with this method. The first challenge is the creation of crystals from DNA molecules in the output, which has led to the impossibility of cascading. The second challenge of this method is the uncontrollability of the reactions of the tiles, which increases the percentage of computing errors. In this article, these two challenges have been solved by changing the structure of leading tiles so that without the activator strand, tiles remain inactive and cannot be connected to other tiles. Also, when the tiles are activated, single-strand DNA will be released after connecting to other tiles, which will be used as the output of the circuit. This output gives the possibility of cascading to self-assembly designed circuits. The method introduced in this article can be a beginning for the re-development of DNA-based circuit design with the self-assembly tile method. © 2007-2012 IEEE.
Computers and Electrical Engineering (00457906)113
Today's processing applications require frequent and energy-consuming data transfers between memory and processing elements. Reducing the dimensions of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) brings essential problems. Therefore, applying emerging technologies should be considered as a solution. As a crossbar array compatible technology, memristors can play the computing and memory device roles. Therefore, it is suitable for In-Memory Computing (IMC). The issue of changing the computation method to achieve higher efficiency can also be considered. Today, approximate computing is of great interest for error-tolerant applications. These two concepts are applied, and an approximate serial full adder based on the Material Implication (IMPLY) method is introduced. The proposed Serial Approximate Full Adder using NAND gates (SAFAN) reduces the number of steps and energy consumption by up to 30% and 26% compared to approximate ones, 70% and 68% compared to exact ones, respectively. The error analysis results show that the accuracy decreases to a reasonable level by applying the SAFAN to the least significant bits (LSBs) of an approximate 8-bit adder. Image analysis criteria evaluated the functionality of the SAFAN in image processing applications, and the results showed the suitable performance of the SAFAN in error-tolerant applications. © 2023
Journal of Supercomputing (15730484)80(3)pp. 3694-3712
Approximate computing is a new approach to reducing power consumption and complexity, increasing performance, and can generate a trade-off between accuracy and power-delay-area efficiency in error-resilient applications. As multiplication is applied in multimedia processing, and it is time-consuming, implementing efficient circuits for multipliers is essential. This article presents novel recursive approximate multipliers and new approximate multipliers based on partial products grouping (clustering). These proposed approximate multipliers are applied in the structure of error-resilient image processing applications: image multiplication, image sharpening, and smoothing. Application-level simulation results show that the proposed multipliers improve the accuracy of their counterparts, while the circuit-level simulation results demonstrate acceptable delay and power consumption. Three Figures Of Merit (FOMs) were introduced to compromise between circuit evaluation criteria and error analysis metrics. By examining these FOMs, the proposed circuits have created a suitable trade-off between circuit and error evaluation criteria compared to other circuits. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a one-to-one mapping between input and output patterns. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Some quantum signal processing applications like filters and image processing applications require the results of arithmetic operations to be saturated. Saturation occurs when adding two numbers with the same sign and this can be done through a quantum saturating adder. This paper proposed a reversible quantum saturating adder with efficient quantum criteria like quantum cost, number of ancilla, and number of garbage outputs. We firstly propose a reversible n-bit quantum saturation generator block which is applied to a quantum adder and construct a quantum saturating adder circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 18% and 33% improvement in quantum cost and garbage outputs, compared to its counterpart, respectively. ©2024 IEEE.
Quantum Information Processing (15700755)23(7)
Quantum circuits are one of the best platforms to implement quantum algorithms. Concerning fault-tolerant quantum circuit, the Clifford + T gate set supports quantum circuits against decoherence error. However, they cause physical resource overheads like many qubits and the use of T gates as a high-cost computing element. This work focuses on low T-cost fault tolerant quantum ALU implementation using Clifford + T gate set. Three new different designs of quantum ALU are proposed by introducing a new quantum logic unit, and new low-cost fault tolerant implementations of full adder and subtractor circuits. We present a novel lemma in synthesizing quantum NCV-based circuits to Clifford + T quantum circuits. This lemma shows how an NCV-based structure with less CNOT layer can lead to an improvement in T-count and T-depth criteria in Clifford + T equivalent circuit. We analyze the effect of applying our proposed lemma in implementing low-cost fault tolerant Clifford + T circuits by some examples on adder and subtractors and ALUs. Comparison of the designs shows 50%, 40%, 36%, and 69% superior functionality of our proposed ALU module in terms of T-count, T-depth, number of qubits, and number of calculated operations compared to the existing counterpart, respectively. The proposed lemma can be used as a simplification step in quantum circuit synthesis algorithms and can be extended to use in quantum synthesis tools. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
IEEE Transactions on Emerging Topics in Computing (21686750)12(3)pp. 918-923
Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases. © 2013 IEEE.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (21563357)13(1)pp. 175-188
The barriers to improving computers' performance have led to the emergence of new computing paradigms and technologies. Among these, the memristors are of great concern. In addition to storing data, memristors can perform logical operations and are proper for In-Memory Computation (IMC). Furthermore, approximate computing is an emerging paradigm introduced to improve performance by reducing the accuracy of calculations in error-resistant applications. These two concepts are combined and presented in four serial Material Implication (IMPLY)-based approximate full adders. In addition, to the positive features of the serial method, the proposed circuits reduce the number of calculation steps by 7%-43%, and the energy consumption improves by 56%-68% compared to the existing exact full adders. The accuracy loss of proposed circuits in different simulated scenarios combining exact and approximate adders are analyzed. Four different image processing applications are applied to ensure the proper functionality of the proposed circuits. The results indicate that in most scenarios, the quality of the images is acceptable, and the Peak Signal-to-Noise Ratio (PSNR) criterion is more than 30 dB. © 2011 IEEE.
Proceedings - IEEE International Symposium on Circuits and Systems (02714310)2022pp. 3115-3119
Approximate computing is a new way of performing calculations in digital systems. By applying this method, performance metrics, e.g., speed, are improved, but in return for this, the accuracy of the calculations is reduced. Memristors are electrical elements that can be used to perform logical calculations along with data storage. This makes memristors a good choice for In-Memory Computation (IMC). IMPLY logic is the first stateful logic proposed for memristive IMC. Approximate computing in memory, particularly using memristive stateful logic, has not been explored yet. In this paper, we combine these two concepts and propose a novel algorithm for serial IMPLY-based adders to implement an approximate full-adder. The proposed approximate full-adder was assessed in an image processing application, and image quality metrics like Peak Signal to Noise Ratio (PSNR) were calculated. In addition, different error quality metrics like Error Distance (ED) and Mean ED (MED) were assessed. Our study shows that the proposed method can achieve up to 40% improvement whereas maintaining the introduced error in an acceptable range (i.e., a PSNR above 32.4). © 2022 IEEE.
Sustainable Computing: Informatics and Systems (22105379)30
In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72% improvement). The proposed cell simulated in HSPICE with 32nm CMOS technology in four different scenarios. First, the proposed cell was assessed as a 1-bit full adder cell; second, the proposed cell applied in a 4-bit carry ripple adder structure. In the third and fourth scenarios, the proposed cell's power consumption and performance were assessed in different power supply voltages, temperatures, and a larger load capacitor. Approximate computing is a design paradigm that is applicable in image processing as an error-resilient application. MATLAB exploited to assess the proposed approximate full adder in image addition application in three different scenarios. The outputs evaluated by different image quality metrics (such as peak signal to noise ratio (PSNR)) and the final outputs of approximation are acceptable in this application due to image quality metrics. © 2021 Elsevier Inc.
Considering the constraints of CMOS technology progress at the nano-domain, memristor technology is one of the preferred alternatives to merge with and substitute CMOS-based memory circuits. At the same time to increase the bandwidth of memories, increase storage density and decrease the interconnection complexity of circuits, multiple-valued logic (MVL) based circuit memories are being introduced as an efficient alternative. As resistive random access memory (ReRAM) is a non-volatile memory and memristor cells allow analog multilevel behavior, they are suitable device to store multiple-level bits of information. Different sources of noise and perturbances may affect the original values of data during the transferring and storing processes. A hybrid scenario based on CMOS and memristor technology is proposed here to recover the stored multiple noisy-perturbed values of resistive random-access memory in an efficient way. To show the correctness of the proposed method, affected images are simulated with Matlab software at system level showing its efficiency. © 2020 IEEE.
IEEE Access (21693536)8pp. 58585-58593
The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively. © 2013 IEEE.
AEU - International Journal of Electronics and Communications (16180399)117
In recent decades, due to the problems with the use of MOSFET transistors in Nanoscale, various alternatives have been introduced. Among them, CNTFET transistors are much more attractive due to their structural and behavioral similarities to the MOSFET transistors. Besides, using binary logic has made some issues that can be solved by applying multiple-valued logic. CNTFETs are also more suitable than MOSFETs in MVL circuits since their threshold voltage can be changed through a change of nano diameter. In this article, newly quaternary half-adder and single-digit multiplier through applying CNTFET technology based on the newly decoder and multiplexer are presented. Simulation of proposed designs is done with Synopsys HSPICE using 32 nm Stanford compact model. The functional results indicate the correct and perfect operation of all designs. Also, compared to some recent designs in literature, obtained 81.34% and 74.07% improvement in PDP for the half-adder and the multiplier designed, respectively. The simulation results under various load capacitors, supply voltage, process variations, frequency, and temperature confirm the stable operation of proposed designs. © 2020 Elsevier GmbH
Full adders are the main block in digital arithmetic. Multipliers, subtractors, and dividers use these blocks as the fundamental part. Approximate computing is a promising method for designing low-power and fast digital circuits, applicable in error resilient applications such as image processing. In this paper, a new current mode logic (CML) approximate full adder proposed. Circuit-level simulation performed by HSPICE applying 32nm Carbon Nanotube Field Effect Transistor (CNTFET) Stanford model. The analysis shows that the proposed circuit's power consumption and delay are highly acceptable, while its error distance (ED) is minimum. The application-level simulation shows that this full adder's peak signal to noise ratio (PSNR) and structural similarity index (SSIM) are the highest among the previous CML approximate full adders. © 2020 IEEE.
MICROELECTRONICS JOURNAL (00262692)85pp. 62-71
CNFETs (Carbon Nanotube Field Effect Transistors) are among the most outstanding candidates to replace with current semiconductor technology. The facing challenges of this newly introduced nanotechnology like metallic CNT (Carbon nanotube) and misaligned and mispositioned CNTs are considered as obstacles in mass production of circuits based on CNFET. In the present article, first, the correlation between methods of CNFET-based designs circuits and misalignment and mispositioning of CNTs occurrence are assessed in the fabrication phase, and then an approach is propose, which may deal with and eliminate the effects of this challenge. This method is introduced at design level, which is immune against misaligned and mispositioned CNTs and due to the lack of complexity in its layout, it is compatible with recent techniques in eliminating metallic CNT, in a sense that, the application of such techniques does not require change in layout. To evaluate circuit parameters in circuits designed with this proposed method, together with evaluating their tolerance against variations in CNT diameter and density and supply voltage variation a full adder is designed based on this proposed method. The various simulations prove the efficiency of this proposed method and the improvement of circuit parameters compared to previous studies. © 2019 Elsevier Ltd
International Journal of Electronics (13623060)106(5)pp. 691-706
Power consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and power-delay-area efficiency in error resilient applications. According to Moore’s law together with CMOS problems in nanoscale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promising. As multiplication is frequently applied in multimedia processing, implementing efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers’ performance. A new 12-transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in terms of area, power consumption, accuracy and reliability design, is more efficient than its existing counterparts. © 2018, © 2018 Informa UK Limited, trading as Taylor & Francis Group.
Microelectronic Engineering (01679317)215
Carbon Nanotube Field Effect Transistor (CNTFET)s are applied instead of silicon transistors to conquer the constraint of MOSFETs in nano-scale, with improving the power consumption and performance. Full adder is one of the basic arithmetic operations to construct large computing systems like multiplication. Due to its widespread application, its optimal design with CNTFET technology is very useful. The contribution here is to propose a high performance CNTFET-based full adder which optimizes the delay and PDP in relation to the previous works in different voltage supply and load capacitance. To show the performance and applicability of this proposed design in large computing systems, three different carry ripple, skip and select adders, all with 4, 8 and 16 size bits are designed and simulated through HSPICE and 32 nm CNTFET technology. The obtained results indicate the advantage of this proposed CNTFET-based full adder. © 2019 Elsevier B.V.
Journal of Nano- and Electronic Physics (20776772)10(2)
Multiplication is an essential part of digital arithmetic, due to its application in video and voice processing, FIR filters, cryptography and other related concepts. Reducing the power consumption and increasing the speed of multipliers will affect the performance of any VLSI system. An approach to accomplish the desired objective for the researchers is applying nano-technologies in implementing VLSI circuits. Carbon nanotube technology is an appropriate option among emerging nano-devices, due to its similarities to the preceding technology, MOSFET. Three new architectures are proposed for a four-bit four-operand multiplier. These multipliers and the conventional four-bit four-operand multiplier are designed, implemented and simulated through carbon nanotube field effect transistors. Evaluations and comparisons are run through HSPICE simulator, through using carbon nanotube technology. These multipliers outperform the common four-operand multiplication run on computers nowadays, referred to as conventional multiplier in this article. © 2018 Sumy State University.
International Review on Computers and Software (discontinued) (18286003)11(6)pp. 566-572
A model is presented here for the customization of RUP methodology in the critical safety systems. The RUP methodology is studied and applied as a reference for the customization. A comprehensive study for the research and the identification of the critical safety systems is conducted. The expansion of critical safety systems and their necessary involvement in different phases and stages regarding product development is essential. There exists much methodology to expand safe software for safety-critical systems based on objective orientation, which can be used in customization of RUP. The Eclipse Process framework is introduced for the customization studied in the presented paper. © 2016 Praise Worthy Prize S.r.l. - All rights reserved.
MICROELECTRONICS JOURNAL (00262692)53pp. 156-166
A new voltage mode design is presented for quaternary logic using CNTFETs. This architecture with presentation of a new structure for voltage division can be applied on any four-valued logic implementation. To ensure the functionality of this promising proposed architecture, basic gates, half-adder, and full-adder are implemented using voltage divider. Moreover, a decoder is considered to enhance the parameters of half-adder such as power consumption, delay, and number of transistors. The designs are simulated using Hspice simulation tool. In comparison with prior works, our half-adder design is optimized by 75.2%, 7.8% and 77% in power consumption, delay and PDP parameters, respectively. © 2016 Elsevier Ltd. All rights reserved.
IEICE Transactions on Electronics (09168524)95(4)pp. 744-751
The reduction in the gate length of the current devices to 65 nm causes their I-V characteristics to depart from the traditional MOS-FETs. As a result, manufacturing of new efficient devices in nanoscale is inevitable. The fundamental properties of the metallic and semi-conducting carbon Nanotubes (CNTs) make them alternatives to the conventional silicon-based devices. In this paper an ultra high-speed and energy-efficient full adder is proposed, using Carbon Nanotube Field Effect Transistor (CN-FET) in nanoscale. Extensive simulation results using HSPICE are reported to show that the proposed adder consumes lower power, and is faster compared to the previous adders. © 2012 The Institute of Electronics, Information and Communication Engineers.
