Energy minimization in the STT-RAM-based high-capacity last-level caches

Abstract

Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches (L3Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM L3Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based L3C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.