Evolvable hardware architectures on FPGA for side-channel security

Abstract

This paper proposes the use of Evolvable Hardware (EH) architectures as a countermeasure against power analysis attacks. It is inspired by the work of Sasdrich et al., in which the block cipher PRESENT is protected against power analysis attacks through the use of dynamic logic FPGA reconfiguration. The countermeasure consists of splitting the substitution boxes (S-boxes) into two parts with a register in between; the way the S-boxes are split is random and is altered before each new execution of the block cipher. This makes it very difficult (or even impossible) for an attacker to perform a Differential Power Analysis (DPA) attack by collecting many power traces of the same implementation. Whereas the approach of Sasdrich et al. requires the external computation and communication of new configurations, our approach computes new configurations on the fly with an on-chip configuration generator based on evolutionary algorithms. This reduces the risk of an adversary tampering with the configuration data and takes away the communication delay. Our work is the first to propose the use of EH and Genetic Programming (GP) for this type of countermeasure. More precisely, we explore two methods, Genetic Programming (GP) and Cartesian Genetic Programming (CGP) and we evaluate the feasibility of these methods by measuring the overhead in terms of delay and resource occupation for the block ciphers PRESENT and PRINTcipher. © Springer Nature Switzerland AG 2020.