Reversible multiplier with a column-wise structure and a reduced number of ancilla inputs and garbage outputs

Abstract

The design of a reversible multiplier is very important due to its wide range of applications in implementing computing systems using new technologies. In most multipliers presented so far, partial product generators and adders are designed separately. This increases the number of blocks that make up the final circuit. Reversible circuits have to use ancilla inputs and garbage outputs. The more blocks in a circuit, the greater the number of inputs and outputs. In this study, a column-wise structure is designed for the multiplier to reduce the number of individual blocks making it up. Increasing the size of reversible circuits in most new technologies is very costly. The number of blocks of the structure presented in this paper for a reversible multiplier is significantly reduced compared to existing designs. Moreover, the number of ancilla inputs and garbage outputs in each of these blocks is minimized. Therefore, the values of these criteria in the proposed multiplier are much lower than those of the previous works. In the proposed method, instead of designing the multiplier in two separate steps, each multiplier column is designed in the form of a block. Therefore, the number of blocks that make up the circuit is equal to the number of the columns of the multiplication operation. As a result, the number of ancilla inputs and garbage outputs is reduced by up to 66% compared to previous works. This column-wise structure is provided for multiplying two 4-bit numbers; however, it is also scalable for designing larger multipliers. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.