Design of energy-efficient and high-speed hybrid decimal adder

Abstract

Decimal computations have attracted a lot of attentions in computer science in recent years due to the increasing significance of decimal-based financial and commercial applications. Addition, a fundamental arithmetic operator, is crucial for performing more complex functions like multiplication and division. Thus, designing an efficient decimal addition method is essential for improving the overall performance of decimal systems. In response, this paper introduces a new hybrid decimal adder. The proposed adder integrates the Carry Skip adder with the Carry Select adder to improve delay, power consumption and area metrics. Simulations and comparisons with recent state-of-the-art Binary Coded Decimal adders highlight the advantages of our design in terms of Power-Delay Product (PDP) and Area-Delay Product (ADP). The proposed adder achieves a 62.25% reduction in PDP and a 48% reduction in ADP. Experiments and simulations were carried out using VHDL and ModelSim SE 10.6f on 90 nm CMOS technology. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.