Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches

Abstract

Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chipcaches due to high density, low static power consumption and scalability. However, this technology suffers from long latency andhigh energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendlymemory technology such as static random access memory along with STT-RAM technology. The proper allocation of datablocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation andmigration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP)formulations. The authors propose an ILP model with three different objective functions which include minimising accesslatency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILPmodel obtains better results in terms of energy consumption and performance compared to the existing hybrid cachearchitecture. © The Institution of Engineering and Technology 2020.