Design and FPGA implementation of a pseudo random bit generator using chaotic maps

Abstract

In this paper, a random bit sequence generator based on chaotic maps is introduced and implemented. In this generator, two chaotic map functions with two different keys are used. The Bifurcation diagram is used to calculate the initial state of the chaotic maps in order to produce the output random bit sequence. Chaotic Logistic and Tent maps classically are defined in an analogue space. In order to implement these chaotic maps on a hardware digital platform, these chaotic maps are modified. Digital chaotic Logistic and Tent maps are introduced. A design for implementation of these modified chaotic maps is also presented. The output bits of two chaotic maps are EX-ORed to produce a random sequence of 1 000 000 bits. These designs are implemented on Field Programmable Gate Array, and the results are reported. The proposed designs are tested by producing 100 samples of 1 000 000 bits, and they pass the standard Federal Information Processing Standard 140-1 and National Institute of Standards and Technology statistical tests for random bit generators. © 2013 by the IETE.