Articles
Electronics (Switzerland) (20799292)13(7)
Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V. © 2024 by the authors.
Mahboob sardroudi, F.,
Habibi M.,
Moaiyeri, M.H.,
Mahboob sardroudi, F.,
Habibi, M.,
Moaiyeri, M.H. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025
Recently, approximate computing and dynamic logic design techniques have been shown to be effective for energy consumption reduction in the design of CNFET -based ternary arithmetic circuits, such as ternary half adders, 1-trit multipliers, and full adders. In this paper, the use of such a design strategy is studied in order to design other large computational blocks. Due to the long delay paths in these large computational circuits, further modifications in the logic can enhance the performance in some scenarios. Subsequently, a dynamic ternary approach is presented, which can break the pass transistor path and improve the performance in long delay chains. The proposed circuit designs of an approximate dynamic ternary full adder and a 4:2 dynamic ternary compressor work correctly under various supply voltages, temperatures, and fan outs. HSpice simulations using the 32 nm Stanford CNFET model, also show a 10% to 85% reduction in energy usage or PDP and 24% to 86% improvement in terms of EDP, respectively compared to previous methods. The proposed circuits NED, MED, PSNR, and SSIM in image multiplication have also been acceptable regarding previous research. © 2024 IEEE.
