A Low-Input Capacitance 12-bit SAR ADC for use in Self-Powered IoT Nodes

Abstract

A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits a structure with separate sample & hold and DAC blocks, separated block SAR, to achieve low-input capacitance. In this structure, the comparator input common-mode voltage is variable and, therefore, a rail-to-rail comparator with rail-to-rail offset cancellation is proposed to cancel the input common-mode dependent offset. The proposed comparator is modified to overcome the uneven distribution of kickback noise too. In order to achieve a 12-bit resolution, the bootstrapped switch is modified. With the aid of the proposed offset cancellation, kickback noise reduction, and switch, the ADC achieves 11.08bit ENOB and the input capacitance is reduced to 2 pF, leading to relatively low input power consumption with no need for a reference supply voltage.