Publication Date: 2015
Computers and Electrical Engineering (00457906)46pp. 303-313
Content-based image retrieval systems are designed to retrieve images based on the high-level desires and needs of users. However, due to the use of low-level features, image retrieval systems are faced with the so-called semantic gap problem in describing high-level concepts. In order to address this critical problem, a new concept-based model is proposed in this paper. The proposed model retrieves images based on two conceptual layers. In the first layer, the object layer, the objects are detected using the discriminative part-based approach. The second layer, on the other hand, is designed to recognize visual composite, a higher level concept to specify the related co-occurring objects. In the proposed model, this concept is recognized by a new template structure including the appearance filters, constraints, and a set of parameters trained by latent SVM. Experiments are carried out on the well-known Pascal VOC dataset. Results show that the proposed model significantly outperforms the existing content-based approaches. © 2015 Elsevier Ltd.
Publication Date: 2023
Computer Networks (13891286)224
The traditional method of saving energy in Virtual Machine Placement (VMP) is based on consolidating more virtual machines (VMs) in fewer servers and putting the rest in sleep mode, which may lead to the overheating of servers resulting in performance degradation and cooling cost. The lack of an accurate and computationally efficient model to describe the thermal condition of the data center environment makes it challenging to develop an effective and adaptive VMP mechanism. Although recently, data-driven approaches have acted successfully in model construction, the shortage of clean, adequate, and sufficient amounts of data put limits their generalizability. Moreover, any change in the data center configuration during operation, makes these models prone to error and forces them to repeat the learning process. Thus, researchers turn to applying model-free paradigms such as reinforcement learning. Due to the vast action-state space of real-world applications, scalability is one of the significant challenges in this area. In addition, the delayed feedback of environmental variables such as temperature give rise to exploration costs. In this paper, we present a decentralized implementation of reinforcement learning along with a novel state-action representation to perform the VMP in the data centers to optimize energy consumption and keep the host temperature as low as possible while satisfying Service Level Agreements (SLA). Our experimental results show more than 17% improvement in energy consumption and 12% in CPU temperature reduction compared to baseline algorithms. We also succeeded in accelerating optimal policy convergence after the occurrence of a configuration change. © 2023 Elsevier B.V.
One of the attacks in the RPL protocol is the Clone ID attack, that the attacker clones the node's ID in the network. In this research, a Clone ID detection system is designed for the Internet of Things (IoT), implemented in Contiki operating system, and evaluated using the Cooja emulator. Our evaluation shows that the proposed method has desirable performance in terms of energy consumption overhead, true positive rate, and detection speed. The overhead cost of the proposed method is low enough that it can be deployed in limited-resource nodes. The proposed method in each node has two phases, which are the steps of gathering information and attack detection. In the proposed scheme, each node detects this type of attack using control packets received from its neighbors and their information such as IP, rank, Path ETX, and RSSI, as well as the use of a routing table. The design of this system will contribute to the security of the IoT network. © 2021 IEEE.
Wireless sensor networks are composed of sensors with low computational and energy resources. Transmission of data is one of the most energy consuming operations in such networks. In-network data aggregation is a popular technique which is performed to reduce data transmissions. However, by aggregating multiple data into one, the security of them is no longer guaranteed. While concealed data aggregation methods have been recently proposed to provide energy efficient, end-to-end confidentiality, not much work has been done to enhance them with aggregate integrity. In this work, we propose a scalable and energy efficient bihomomorphic method to preserve end-to-end confidentiality and aggregate integrity against outsider attacks. A distributed validation scheme is used to prevent blind rejection caused by outsiders. To provide better resilience, a key refreshment method is used to prevent analysis attacks. © 2011 IEEE.
Publication Date: 2023
Quantum Information Processing (15700755)22(4)
The reversible multipliers are of significant importance in implementing the computational systems by the novel technologies. The generation section of partial products and adders existing in the provided multipliers so far is designed separately. This increases the constituent blocks’ number of the final circuit. As the constituent number of blocks in a circuit increases, the number of inputs and outputs rises. The enhancement of the reversible circuits will be costly in most novel technologies. In this study, a structure is provided for the n× n quantum multipliers, where the number of constituent blocks is significantly declined compared to the existing designs. Also, the number of ancilla inputs and garbage outputs is at the minimum level in each block. In the provided method of this article, each multiplier column has been designed in the form of a block (instead of the multiplier design in two separate steps). Also, a method is provided for making the circuit fault-tolerant. In this case, instead of using the fault-tolerant gates in the multiplier design process, first, the circuit is designed regularly, and ultimately, the fault tolerance is added to it. Accordingly, the number of ancilla inputs and garbage outputs of the regular quantum multiplier is decreased by 66% and 70%, respectively, compared to the previous works. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2015
Journal of Supercomputing (15730484)71(8)pp. 3116-3148
Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previousworks onWNoC systems. In this article, a fault-tolerant hierarchical hybridWNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. © Springer Science+Business Media New York 2015.
Publication Date: 2019
IEEE Transactions on Circuits and Systems II: Express Briefs (15583791)66(1)pp. 146-150
2-D convolution has been used as a subsystem for filtering and enhancement in a wide range of signal and image processing applications. It is not only a memory intensive operation but also a compute intensive process. The previous efforts to improve the performance of 2-D convolution have primarily focused on the memory access challenges. However, the convolver's performance is highly dependent on the efficient design of the computation units, which can be enhanced significantly by employing some techniques such as pipelining. In this brief, a pipelined with low pixel access rate architecture for implementation of 2-D convolution is presented. Compared to the conventional convolvers, the proposed design involves a fixed (independent to the problem/kernel) size, and a significantly shorter critical path specifically for large kernel sizes where the proposed convolver works with 283-MHz clock frequency, on a Xilinx Virtex-7 (XC7V2000t) field-programmable gate array, for a {3\times 3} kernel. Additionally, the required pixel access rate of the new scheme is less than that of the state-of-The-Art methods, which is only 849 Mb/s for a {3\times 3} kernel and 8-bit pixels. The improvements in the critical path delay and the required pixel access rate are obtained without significant increase in the resource utilization. © 2004-2012 IEEE.
Industrial control systems (ICS) are applied in many critical infrastructures. Reducing reconfiguration time after hazard leads to safety improvement, so it is one of the most important objectives in these systems. Hazards can be due to the 'system failure' or 'cyber-attacks' factors. One of the procedures that can reduce the reconfiguration time is determining as soon as possible the cause of hazards based on the above mentioned factors. Differentiation of attack from failure without redundant data in addition to data from the system sensors is not possible. With advent of the IoT as IIoT, a condition is developed to provide the required redundant data; however, by increasing the number of IIoT devices within a factory, the generated data volume becomes too large. In this paper we describe a fog-based approach applied in a factory to deal with such increasing complexity. We compare the proposed method with a traditional cloud-based solution. According to the results, the proposed method leads to a reduction of 60% lost time in the recovery reconfiguration step of the system. © 2020 IEEE.
Publication Date: 2018
Computers and Education (0360-1315)120pp. 75-89
The quality of online information is highly variable because anyone can post data on the internet, and not all online sources are equally reliable, valuable, or accurate. Previous studies reveal problems with online information evaluation skills and a lack of ability in using evaluation criteria, including currency, relevance, authority, accuracy and purpose. The primary purpose of this study is to develop a framework for cooperative and interactive mobile learning to improve students' online information evaluation skills. A mobile learning application is subsequently developed based on the proposed framework. To assess the effectiveness of the developed application, an experiment is conducted on diploma students in a university. A usability questionnaire is conducted on an experimental group to identify students' perceptions regarding the usability of the developed mobile application. The experimental results indicate that the application is significantly more effective with an effect size of 1.91 in improving students’ online information evaluation skills than traditional learning. The results contribute to the extant literature in the context of mobile learning by identifying usability evaluation features and providing a framework for developing cooperative and interactive mobile learning. The implications of the present findings for research and instructional practice are discussed. © 2018 Elsevier Ltd
Publication Date: 2013
International Journal Of Communication Networks And Information Security (20760930)5(2)pp. 93-103
The 802.11 families are considered as the most applicable standards for Wireless Local Area Networks (WLANs) where nodes make access to the wireless media using random access techniques. In such networks, each node adjusts its contention window to the minimum size irrespective to the number of competing nodes. So in the case of large number of nodes, the network performance is reduced because of raising the collision probability. In this paper, a game theory based method is being proposed to adjust the users' contention window in improving the network throughput, delay and packet drop ratio under heavy traffic load circumstances. The system performance, evaluated by simulations, shows some superiorities of the proposed method over 802.11-DCF (Distribute Coordinate Function.
Publication Date: 2019
Journal Of Information Systems And Telecommunication (23221437)7(1)pp. 12-22
IEEE 802.11e is standardized to enhance real-time multimedia applications' Quality of Service. This standard introduces four access categories for different types of applications. Each access category has four adjustable parameters: Arbitrary Inter-Frame Space Number, minimum Size of Contention Window, maximum size of Contention Window, and a Transmission Opportunity limit. A Transmission Opportunity limit is the time interval, in which a wireless station can transmit a number of frames consecutively, without releasing the channel and any further contention with other wireless stations. Transmission Opportunity improves network throughput as well as service differentiation. Proper Transmission Opportunity adjustment can lead to better bandwidth utilization and Quality of Service provisioning. This paper studies the dynamic adjustment of Transmission Opportunity in IEEE 802.11e using a game-theory based approach called Game Theory Based Dynamic Transmission Opportunity. Based on the proposed method, each wireless node chooses its appropriate Transmission Opportunity according to its queue length and media access delay. Simulation results indicate that the proposed approach improves channel utilization, while preserving efficiency in WLANs and minimizing selfishness behaviors of stations in a distributed environment. © 2019 Iranian Academic Center for Education, Culture and Research.
Publication Date: 2012
Applied Intelligence (0924669X)36(3)pp. 685-697
Predicting the next movement directions, which will be chosen by the vehicle driver at each junction of a road network, can be used largely in VANET (Vehicular Ad-Hoc Network) applications. The current methods are based on GPS. In a number of VANET applications the GPS service is faced with some obstacles such as high-rise buildings, tunnels, and trees. In this paper, a GPS-free method is proposed to predict the vehicle future movement direction. In this method, vehicle motion paths are described by using the sequence of turning directions on the junctions, and the distances between the junctions. Movement patterns of the vehicles are extracted through clustering of the vehicle's motion paths using SOM (Self Organizing Map). These patterns are then used for predicting the next movement direction, which will be chosen by the driver at the next junction. The obtained results indicate that our GPS-free method is comparable with the GPS-based methods, while having more advantages in different applications regarding urban traffic. © 2011 Springer-Verlag.
Yazdinejad, A.,
Parizi, R.M.,
Bohlooli, A.,
Dehghantanha, A.,
Choo, K.R. Publication Date: 2020
Journal of Network and Computer Applications (10848045)156
The emergence of new network technologies and users' ever-increasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the high-level P4 language is applied to allow the description of its register-transfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through pre-processing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320 MHz clock speed, which in comparison with NetFPGA-10G, NetFPGA-SUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex-7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flip-flops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures. © 2020 Elsevier Ltd
Publication Date: 2025
European Physical Journal Plus (21905444)140(8)
Researchers and designers should face the challenges caused by memory and energy limitations. Quantum-dot Cellular Automata (QCA) offers a promising alternative with its high speed and low power consumption for dense emerging nano-electronic structures. Applying the approximate computing paradigm, where lower hardware complexity is prioritized over complete accuracy, can reduce power consumption. Integrating approximate computing with QCA reduces energy consumption and enhances system performance, although at the potential cost of reduced accuracy. The arithmetic unit is responsible for binary addition, subtraction, and multiplication. This article proposes a methodology for integrating QCA-based gates with approximate computing to achieve high-speed computation while minimizing resource usage. Additionally, it introduces a novel high-speed and cost-efficient design for a QCA-based approximate full adder, demonstrating improved hardware evaluation metrics, including delay, energy consumption, and acceptable error margins. The cost analysis indicates that the proposed design effectively balances circuit design trade-offs, particularly regarding delay and area. The functionality validation of the proposed circuit is assessed by the QCADesigner-E tool. Compared to the state of the art, the proposed design enhances performance metrics, achieving average improvements of 50% in delay, 26% in the number of QCA cells, and 78% in cost. These advancements are significant for the development of efficient and cost-effective QCA-based systems. Various error evaluation metrics assess the proposed approximate full adder's computational accuracy across three implementation scenarios of the 8-bit approximate adder architecture. Application-level simulation outputs show that the proposed circuits perform well in all scenarios, with the Peak-Signal-to-Noise Ratio (PSNR) exceeding 30 dB. © The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2025.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively. © 2024 IEEE.
Publication Date: 2019
Visual Computer (14322315)35(10)pp. 1373-1391
Image rotation and scale change can significantly degrade the efficiency of local descriptors in blurred image matching. Conventional local image descriptors often only employ the rectangular gradient information of detected region around each interest point. Due to unwanted errors estimated for scale and dominant orientation, the performance of these local descriptors is severely degraded when applied to blurred images. To solve this problem, we propose a novel descriptor called radial and angular gradient intensity histogram (RAGIH) which jointly utilizes gradient and intensity features. In this local descriptor, feature vectors are extracted from two concentric circular regions around each key point and using angular and radial gradients in a specific local coordinate system reduces the estimation errors. Extensive experiments on challenging Oxford dataset demonstrate the favorable performance of our descriptor compared to state-of-the-art approaches. © 2018, Springer-Verlag GmbH Germany, part of Springer Nature.
Considering the constraints of CMOS technology progress at the nano-domain, memristor technology is one of the preferred alternatives to merge with and substitute CMOS-based memory circuits. At the same time to increase the bandwidth of memories, increase storage density and decrease the interconnection complexity of circuits, multiple-valued logic (MVL) based circuit memories are being introduced as an efficient alternative. As resistive random access memory (ReRAM) is a non-volatile memory and memristor cells allow analog multilevel behavior, they are suitable device to store multiple-level bits of information. Different sources of noise and perturbances may affect the original values of data during the transferring and storing processes. A hybrid scenario based on CMOS and memristor technology is proposed here to recover the stored multiple noisy-perturbed values of resistive random-access memory in an efficient way. To show the correctness of the proposed method, affected images are simulated with Matlab software at system level showing its efficiency. © 2020 IEEE.
Industry 4.0 provides a framework for applying new technologies in industrial environments to boost the efficiency and intelligence. A recently blossomed technology in Industry 4.0 is Internet of Things (IoT), which allows us to create a smart environment by connecting various equipment. One of the main applications of IoT in a smart factory is to design monitoring systems, which helps put the behavior of devices under permanent and comprehensive supervision. However, the rapid growth and change in the monitoring facilities creates a big challenge for people who either want to use that equipment in Industry 4.0, or want to update the systems to benefit from this technology. To address this problem, this paper presents new approach based on model-driven engineering paradigm, for simplifying the design and development of real-Time monitoring systems in an industrial environment. Our approach includes a domain-specific modeling language, a graphical editor, and model-To-code transformations that generate a hardware descriptive code, a mobile application, and a web application for a monitoring system. To evaluate the applicability of our approach, a scenario in the power industry has been designed, which offers user a VHDL code, a mobile application, and a web application for monitoring processes of the plant. © 2020 IEEE.
Publication Date: 2022
Journal of Supercomputing (15730484)78(2)pp. 2597-2615
Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall performance of image processing applications. In this regard, it is necessary to design of reconfigurable convolver with respect to desired kernel sizes list. In this paper, a novel approach is presented for implementation of an area-efficient reconfigurable convolver with appropriate throughput and convolution computational time for an arbitrary kernel size list. This approach is based on the adjustment of logical blocks arrangement in the conventional convolvers. The feasibility and benefits of the proposed approach are demonstrated through a case study of the design implementation on an FPGA platform using the XILINX ISE software. Compared to the well-known reconfigurable convolvers, the proposed design significantly reduces convolution computational time and improves throughput with a reasonable number of hardware resources. For instance, the proposed reconfigurable convolver only requires 0.38 ms to perform a 3 × 3 convolution on a 268 × 460 image with 8-bit pixels and only occupies 455 slices resource of Xilinx Virtex-4 (XC4VLX25) FPGA, in which the throughput of 324 million outputs per second (MOPS) is provided with 81 MHz clock frequency for kernel size of 3 × 3. On average, the MPOS of the proposed approach is approximately improved by 43.13% in relation to the other considered alternatives. Experimental results confirm that the proposed reconfigurable convolver is a very competitive design among the alternative reconfigurable convolvers. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2019
MICROELECTRONICS JOURNAL (00262692)85pp. 62-71
CNFETs (Carbon Nanotube Field Effect Transistors) are among the most outstanding candidates to replace with current semiconductor technology. The facing challenges of this newly introduced nanotechnology like metallic CNT (Carbon nanotube) and misaligned and mispositioned CNTs are considered as obstacles in mass production of circuits based on CNFET. In the present article, first, the correlation between methods of CNFET-based designs circuits and misalignment and mispositioning of CNTs occurrence are assessed in the fabrication phase, and then an approach is propose, which may deal with and eliminate the effects of this challenge. This method is introduced at design level, which is immune against misaligned and mispositioned CNTs and due to the lack of complexity in its layout, it is compatible with recent techniques in eliminating metallic CNT, in a sense that, the application of such techniques does not require change in layout. To evaluate circuit parameters in circuits designed with this proposed method, together with evaluating their tolerance against variations in CNT diameter and density and supply voltage variation a full adder is designed based on this proposed method. The various simulations prove the efficiency of this proposed method and the improvement of circuit parameters compared to previous studies. © 2019 Elsevier Ltd
Publication Date: 2003
Electric Power Components and Systems (15325016)31(5)pp. 513-524
This paper presents a new model for the identification of the power system transfer functions. The usual model has been to use the shift operator q, or its equivalent z transform, but this gives inaccurate results with the small sampling times that are now used in modern controllers. It is shown by a comparison that this problem can be resolved by using the delta operator δ instead. This is shown by a multimachine example using both operators. The simulation results show that the delta operator formulation reflects the dynamic behavior of the system more accurately. © 2003 Taylor & Francis.
Publication Date: 2021
Journal of Computational Electronics (15698025)20(1)pp. 718-734
The synthesis of reversible circuits is a challenge on which many studies have been conducted. Different algorithms attempt to propose a more optimal implementation for each description of a reversible circuit, using reversible gates. In this paper, an algorithm is proposed which, by a heuristic method using a Simulated Annealing algorithm, tries to find a near-optimal circuit to the given truth table. Unlike previous methods, this method does not necessarily require a correct initial circuit to improve it. It can start from a correct circuit or a near-correct circuit or even from an empty circuit, and tries to get a circuit that is better than the initial circuit. It can also achieve different circuits in different runs that are better than the initial circuit. Finally, from the various circuits that this algorithm has produced in different runs, the best is selected as the final circuit. The proposed algorithm also tries to produce a circuit as simple as possible with respect to don’t-care combinations. Also, the current algorithm does not depend on the type of gates. Any library, including arbitrary reversible gates, can be used in this method. © 2021, Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2023
Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A (02533839)46(2)pp. 107-117
Wireless channels have a broadcast nature based on which opportunistic routing protocols work. In opportunistic routing protocols, packets are forwarded by the intermediate nodes that hear their transmissions, which are called candidate forwarders. In most of these algorithms, the forwarder list is pre-determined. However, the energy-efficient selection of the forwarder list is a research topic that is not considered well. Energy Efficient OPportunistic Routing algorithm (EEOPR) is presented in this paper in which the forwarders are determined on the packets’ fly. EEOPR is a flexible method that performs the routing process locally, and the candidate forwarders are selected during the routing and for each packet. The process of the candidate nodes’ selection and their packet forwarding are managed by the Genetic algorithm according to the nodes’ remaining energy and their regions. Simulation results show that network performance is improved in EEOPR compared to ROMER and CORP-M in terms of throughput, the number of duplicate packets, and the network nodes’ residual energy. © 2023 The Chinese Institute of Engineers.
Publication Date: 2023
Electronics (Switzerland) (20799292)12(5)
Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods. © 2023 by the authors.
Publication Date: 2019
International Journal of Electronics (13623060)106(5)pp. 691-706
Power consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and power-delay-area efficiency in error resilient applications. According to Moore’s law together with CMOS problems in nanoscale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promising. As multiplication is frequently applied in multimedia processing, implementing efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers’ performance. A new 12-transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in terms of area, power consumption, accuracy and reliability design, is more efficient than its existing counterparts. © 2018, © 2018 Informa UK Limited, trading as Taylor & Francis Group.
Publication Date: 2021
Transactions on Emerging Telecommunications Technologies (21615748)32(9)
The femtocell networks have been developed to solve the indoor coverage issues. In the large commercial buildings, finding the minimum number of femtocells and their locations with a full coverage of the building is a complicated problem. This article attempts to minimize the number of femtocells in a large building while providing maximum coverage. In this article, the locations of the femtocells are determined such that the total number of handovers in the building is minimal. For this purpose, the building area is divided into small and equal-sized subregions, and a femtocell matrix coverage is obtained for each subregion using the path-loss equation. We utilize the femtocell matrix coverage and propose a mathematical model to minimize the number of femtocells with a maximum (almost complete) coverage of the building area. We employ the genetic algorithm to solve this NP-hard problem. An efficient algorithm is also presented to create the initial population for the genetic algorithm. Based on the past behavior of the users, we select the locations for the femtocells to reduce the number of handovers. Numerical results indicate that with almost complete coverage, our proposed method reduces the femtocell counts up to 55% and reduces the number of handovers up to 30% compared with the previous work. © 2021 John Wiley & Sons, Ltd.
