منو
مرتب سازی بر اساس: سال انتشار
(نزولی)
Publication Date: 2024
2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025 pp. 146-150
This paper compares two prevalent architectures in systolic arrays: weight stationary and output stationary methods. Systolic arrays utilize interconnected processing elements (PEs) to perform parallel processing, making them suitable for applications in digital signal processing, image processing, and machine learning. We focus on their implementation of 2D matrix multiplication, a fundamental operation in neural networks. Simulations were conducted using Verilog HDL within the Xilinx Vivado Design Suite 2019, employing a 3x1 input matrix and a 3x3 weight matrix. Results confirmed the functionality of both architectures, with output matrices matching expected results. Weight stationary designs minimized data movement, while output stationary designs enhanced throughput through effective input data reuse. Furthermore, this research demonstrates that the critical path remains constant despite increases in the number of processing units, providing valuable insights for future architectural designs. With a critical path delay of approximately 8.8 ns, corresponding to a maximum frequency of about 113 MHz, the study highlights that the critical path remains stable when scaling the number of PEs. Overall, this research validates the effectiveness of both architectures in high-performance matrix operations, offering valuable insights for future systolic array designs. © 2024 IEEE.
Publication Date: 2023
Quantum Information Processing (15700755) 22(4)
The reversible multipliers are of significant importance in implementing the computational systems by the novel technologies. The generation section of partial products and adders existing in the provided multipliers so far is designed separately. This increases the constituent blocks’ number of the final circuit. As the constituent number of blocks in a circuit increases, the number of inputs and outputs rises. The enhancement of the reversible circuits will be costly in most novel technologies. In this study, a structure is provided for the n× n quantum multipliers, where the number of constituent blocks is significantly declined compared to the existing designs. Also, the number of ancilla inputs and garbage outputs is at the minimum level in each block. In the provided method of this article, each multiplier column has been designed in the form of a block (instead of the multiplier design in two separate steps). Also, a method is provided for making the circuit fault-tolerant. In this case, instead of using the fault-tolerant gates in the multiplier design process, first, the circuit is designed regularly, and ultimately, the fault tolerance is added to it. Accordingly, the number of ancilla inputs and garbage outputs of the regular quantum multiplier is decreased by 66% and 70%, respectively, compared to the previous works. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2023
Electronics (Switzerland) (20799292) 12(5)
Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods. © 2023 by the authors.
Publication Date: 2022
Physical Communication (18744907) 55
Femtocells are designed to cover small indoor areas. In commercial buildings, femtocell placement and number is one of the most important network issues. In such buildings, another problem is uneven traffic distribution in different spaces, which causes high traffic and low traffic areas. Due to the small coverage areas of femtocells and these high traffic and low traffic areas, some femtocells are overloaded and some femtocells are underloaded. Also, increase in the distance of high-traffic areas from the femtocells, increases the number of resource blocks used. These issues reduce network efficiency. In this article, femtocell placement has been managed in such a way that the traffic load on the femtocells is balanced and is reduced the number of resource blocks used in the building and efficiency is increased. A mathematical model for femtocell placement has been introduced which balancing the femtocell load and reducing the average number of resource blocks used, the conditions of maximum coverage area and minimum femtocell number should also be fulfilled. This challenge has been addressed by using non-dominated sorting genetic algorithm (NSGA-II). An initial population generation algorithm and a selection function are also presented. The assessment results indicate that compared to the latest studies, this newly proposed method reduces the average load on the whole building by 79% and decreases the load variance between the femtocells by 86%. © 2022 Elsevier B.V.
Publication Date: 2022
Journal of Supercomputing (09208542) 78(1)pp. 315-342
The design of a reversible multiplier is very important due to its wide range of applications in implementing computing systems using new technologies. In most multipliers presented so far, partial product generators and adders are designed separately. This increases the number of blocks that make up the final circuit. Reversible circuits have to use ancilla inputs and garbage outputs. The more blocks in a circuit, the greater the number of inputs and outputs. In this study, a column-wise structure is designed for the multiplier to reduce the number of individual blocks making it up. Increasing the size of reversible circuits in most new technologies is very costly. The number of blocks of the structure presented in this paper for a reversible multiplier is significantly reduced compared to existing designs. Moreover, the number of ancilla inputs and garbage outputs in each of these blocks is minimized. Therefore, the values of these criteria in the proposed multiplier are much lower than those of the previous works. In the proposed method, instead of designing the multiplier in two separate steps, each multiplier column is designed in the form of a block. Therefore, the number of blocks that make up the circuit is equal to the number of the columns of the multiplication operation. As a result, the number of ancilla inputs and garbage outputs is reduced by up to 66% compared to previous works. This column-wise structure is provided for multiplying two 4-bit numbers; however, it is also scalable for designing larger multipliers. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2021
Transactions on Emerging Telecommunications Technologies (21615748) 32(9)
The femtocell networks have been developed to solve the indoor coverage issues. In the large commercial buildings, finding the minimum number of femtocells and their locations with a full coverage of the building is a complicated problem. This article attempts to minimize the number of femtocells in a large building while providing maximum coverage. In this article, the locations of the femtocells are determined such that the total number of handovers in the building is minimal. For this purpose, the building area is divided into small and equal-sized subregions, and a femtocell matrix coverage is obtained for each subregion using the path-loss equation. We utilize the femtocell matrix coverage and propose a mathematical model to minimize the number of femtocells with a maximum (almost complete) coverage of the building area. We employ the genetic algorithm to solve this NP-hard problem. An efficient algorithm is also presented to create the initial population for the genetic algorithm. Based on the past behavior of the users, we select the locations for the femtocells to reduce the number of handovers. Numerical results indicate that with almost complete coverage, our proposed method reduces the femtocell counts up to 55% and reduces the number of handovers up to 30% compared with the previous work. © 2021 John Wiley & Sons, Ltd.
Publication Date: 2021
The Isc International Journal Of Information Security (20082045) 13(2)pp. 157-162
There are many different ways of securing FPGAs to prevent successful reverse engineering. One of the common forms is obfuscation methods. In this paper, we proposed an approach based on obfuscation to prevent FPGAs from successful reverse engineering and, as a result, hardware trojan horses (HTHs) insertion. Our obfuscation method is using configurable look up tables (CFGLUTs). We suggest to insert CFGLUTs randomly or based on some optional parameters in the design. In this way, some parts of the design are on a secure memory, which contains the bitstream of the CFGLUTs so that the attacker does not have any access to it. We program the CFGLUTs in run-time to complete the bitstream of the FPGA and functionality of the design. If an attacker can reverse engineer the bitstream of the FPGA, he cannot detect the design because some part of it is composed of CFGLUTs, which their bitstream is on a secure memory. The first article uses CFGLUTs for securing FPGAs against HTHs insertion, which are results of reverse engineering. Our methods do not have any power and hardware overhead but 32 clock cycles time overhead. © 2020 ISC. All rights reserved.
Publication Date: 2021
The Isc International Journal Of Information Security (20082045) 13(1)pp. 47-57
Nowadays the security of the design is so important because of the different available attacks to the system. the main aim of this paper is to improve the security of the circuit design implemented on FPGA device. Two approaches are proposed for this purpose. The first is to fill out empty space using flip-flops and LUTs so that there is no available space for inserting a hardware Trojan. We name this filling structure as Gate-chain. The second approach increases the security of the implemented design by identifying the low observable/controllable points of the main design and wiring them to the unused ports or the pre-designed Gate-chains. The proposed solutions not only prevent Trojan insertion but also increase the Trojan detection capabilities. Simulation results on Xilinx devices implementing different benchmarks show that the proposed method incurs dynamic power overhead just in test mode with less than one percent of delay overhead for critical path in normal mode. © 2020 ISC. All rights reserved.
Publication Date: 2021
Journal of Computational Electronics (15698025) 20(1)pp. 718-734
The synthesis of reversible circuits is a challenge on which many studies have been conducted. Different algorithms attempt to propose a more optimal implementation for each description of a reversible circuit, using reversible gates. In this paper, an algorithm is proposed which, by a heuristic method using a Simulated Annealing algorithm, tries to find a near-optimal circuit to the given truth table. Unlike previous methods, this method does not necessarily require a correct initial circuit to improve it. It can start from a correct circuit or a near-correct circuit or even from an empty circuit, and tries to get a circuit that is better than the initial circuit. It can also achieve different circuits in different runs that are better than the initial circuit. Finally, from the various circuits that this algorithm has produced in different runs, the best is selected as the final circuit. The proposed algorithm also tries to produce a circuit as simple as possible with respect to don’t-care combinations. Also, the current algorithm does not depend on the type of gates. Any library, including arbitrary reversible gates, can be used in this method. © 2021, Springer Science+Business Media, LLC, part of Springer Nature.
Publication Date: 2019
Journal of Circuits, Systems and Computers (02181266) 28(14)
Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults. © 2019 World Scientific Publishing Company.
Publication Date: 2018
Journal of Circuits, Systems and Computers (02181266) 27(9)
Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans. © 2018 World Scientific Publishing Company.
Publication Date: 2013
Telecommunication Systems (15729451) 52(2)pp. 525-537
We proposed an algorithm to encrypt an image in hybrid domain, frequency and time domains. The proposed method is a private key encryption system with two main units, chaotic phase-magnitude transformation unit and chaotic pixel substitution unit. Chaotic phase-magnitude transformation unit works in frequency domain and a 2-D DFT is performed on the plain image to change the domain. A chaotic function, the tent map, is used to generate the pseudo random image, which are combined with the plain image in frequency domain. Chaotic pixel substitution unit works in time domain Bernoulli map is applied to produce another pseudo random image that is mixing with the encrypted image nonlinearly. The performance of the proposed chaotic image encryption system is analysed using a computer simulation. The distribution of histogram of encrypted image is uniform. Chi-square value for encrypted image of our proposed method is considerably low. The MSE of the proposed encrypted image is big enough. The correlation coefficients of the proposed encrypted image in all three directions are sufficiently small. The total key length is large enough to resist the proposed system against any brute-force attack. The proposed scheme is robust against chosen plaintext attacks too. The proposed chaotic image encryption system, which is used frequency and time domain together, is more secure than most of single domain image encryption systems. © 2011 Springer Science+Business Media, LLC.
Publication Date: 2013
IETE Journal of Research (03772063) 59(1)pp. 63-73
In this paper, a random bit sequence generator based on chaotic maps is introduced and implemented. In this generator, two chaotic map functions with two different keys are used. The Bifurcation diagram is used to calculate the initial state of the chaotic maps in order to produce the output random bit sequence. Chaotic Logistic and Tent maps classically are defined in an analogue space. In order to implement these chaotic maps on a hardware digital platform, these chaotic maps are modified. Digital chaotic Logistic and Tent maps are introduced. A design for implementation of these modified chaotic maps is also presented. The output bits of two chaotic maps are EX-ORed to produce a random sequence of 1 000 000 bits. These designs are implemented on Field Programmable Gate Array, and the results are reported. The proposed designs are tested by producing 100 samples of 1 000 000 bits, and they pass the standard Federal Information Processing Standard 140-1 and National Institute of Standards and Technology statistical tests for random bit generators. © 2013 by the IETE.
Publication Date: 2012
International Journal of Bifurcation and Chaos (02181274) 22(5)
In this paper, we propose a new one-dimensional, two-segmental nonlinear map by combining tent, triangle and parabola curve functions. We call the proposed map, Mehrab map since its return maps shape is similar to an altar (which we call it "Mehrab"). Definition and properties of Mehrab map along with orbit diagrams, Lyapunov exponents, and its histograms are considered. To generate more uniform density function maps, two modified versions of the proposed Mehrab map are also defined. In the first modification of Mehrab map (FMM), vertical symmetry and transformation to the right are used. Sensitivity to initial condition and total chaotic range of FMM are medium. Probability density function of FMM map is uniform and its histograms show this uniformity. In the second modification of Mehrab (SMM) map, vertical and horizontal symmetry and transformation to the right are used. According to the orbit diagrams and Lyapunov exponents, the sensitivity to initial condition and the total chaotic range of SMM map are large. This property gives more chaotic region to the map. Its histograms prove that the probability density function of SMM is also uniform. © 2012 World Scientific Publishing Company.
Publication Date: 2009
Mathematical Problems in Engineering (15635147) 2009
In this paper, we have presented a new permutation-substitution image encryption architecture using chaotic maps and Tompkins-Paige algorithm. The proposed encryption system includes two major parts, chaotic pixels permutation and chaotic pixels substitution. A logistic map is used to generate a bit sequence, which is used to generate pseudorandom numbers in Tompkins-Paige algorithm, in 2D permutation phase. Pixel substitution phase includes two process, the tent pseudorandom image (TPRI) generator and modulo addition operation. All parts of the proposed chaotic encryption system are simulated. Uniformity of the histogram of the proposed encrypted image is justified using the chi-square test, which is less than 2 (255, 0.05). The vertical, horizontal, and diagonal correlation coefficients, as well as their average and RMS values for the proposed encrypted image are calculated that is about 13 less than previous researches. To quantify the difference between the encrypted image and the corresponding plain-image, three measures are used. These are MAE, NPCR, and UACI, which are improved in our proposed system considerably. NPCR of our proposed system is exactly the ideal value of this criterion. The key space of our proposed method is large enough to protect the system against any Brute-force and statistical attacks. © 2009 S. Etemadi Borujeni and M. Eshghi.
Publication Date: 2002
Underwater Technology (17560543) 2002pp. 33-36
It is required a precise, linear indication of the depth of water in a specific part of the sea. This demands a continuous level measurement. There are a wide variety of ways to produce a signal that tracks the depth of water in a specific part of the sea. Ultrasonic detectors find the distance between seabed to the surface of the water. To measure level, depth, with an ultrasonic range detector, the module is mounted at the bottom of the sea, seabed, looking up the surface. We must measure the time between the transmit pulse and the echo received pulses. Since the ultrasonic signal is traveling at the speed of sound, the time between transmission and echo received is a measure of the distance to the surface,water depth. A micro-controller sends a pulse to the ultrasonic module. The module is transmitting an ultrasonic wave for a short period of time and wait for receiving its echo. As soon as echo received to ultrasonic module, is sent a pulse to micro-controller, which measures the time between two pulses. There are two modes of operation, program mode and run mode. When the unit is powered. it is programmed to start up in the run mode, to detect the distance from the transducer face to a target, depth, in meter. The unit can be placed into program mode at any time by pressing the menu key to alter a value of parameters in order to better suit the application or user preferences. Unit of measurement, type of measurement, set point of alarms and factory setting are some of its parameters. The working time of transition and receiver part of the module is specifies by micro-controller normally for each second 10 ultrasonic pulses are transmitted. The measuring error is approximately 1.25%. Such an error value is acceptable with reception to wavelength of ultrasonic waves. For so many application that the precision of Cm is sufficient ultrasonic level measurement is suitable. The system protected from virtual echoed by using threshold and counting number of echo pulses. © 2002 IEEE.
Publication Date: 0
pp. 287-292
Although high-performance artificial intelligence (AI) models require substantial computational resources, embedded systems are constrained by limited hardware capabilities, such as memory and processing power. On the other hand, embedded systems have a broad range of applications, making the integration of AI and embedded systems a prominent topic in both hardware and AI research. Creating powerful speech embeddings for embedded systems is challenging, as such models, like Wave2Vec, are typically computationally intensive. Additionally, the scarcity of data for many low-resource languages further complicates the development of high-performance models. To address these challenges, we utilized BERT to generate speech embeddings. BERT was selected because, in addition to producing meaningful embeddings, it is trained on numerous low-resource languages and facilitates the design of efficient decoders. This study introduces a compact speech encoder tailored for low-resource languages, capable of functioning as an encoder across a diverse range of speech tasks. To achieve this, we utilized BERT to generate meaningful embeddings. However, due to the high dimensionality of BERT embeddings, which imposes significant computational demands on many embedded systems, we applied dimensionality reduction techniques. The reduced-dimensional vectors were subsequently used as labels for speech data to train a model composed of convolutional neural networks (CNNs) and fully connected layers. Finally, we demonstrated the encoder's effectiveness through an application in speech command recognition. © 2024 IEEE.
Publication Date: 2023
Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A (02533839) 46(2)pp. 107-117
Wireless channels have a broadcast nature based on which opportunistic routing protocols work. In opportunistic routing protocols, packets are forwarded by the intermediate nodes that hear their transmissions, which are called candidate forwarders. In most of these algorithms, the forwarder list is pre-determined. However, the energy-efficient selection of the forwarder list is a research topic that is not considered well. Energy Efficient OPportunistic Routing algorithm (EEOPR) is presented in this paper in which the forwarders are determined on the packets’ fly. EEOPR is a flexible method that performs the routing process locally, and the candidate forwarders are selected during the routing and for each packet. The process of the candidate nodes’ selection and their packet forwarding are managed by the Genetic algorithm according to the nodes’ remaining energy and their regions. Simulation results show that network performance is improved in EEOPR compared to ROMER and CORP-M in terms of throughput, the number of duplicate packets, and the network nodes’ residual energy. © 2023 The Chinese Institute of Engineers.
Publication Date: 2021
IEEE Transactions on Network and Service Management (19324537) 18(3)pp. 3918-3932
Congestion control has a vital role in the prosperity of any network. Thus, designing an effective mechanism for congestion control of the NDN is an active research area. In NDN, congestion control and interest forwarding mechanisms are usually considered an integrated plane for the network traffic management. In this paper, we propose to decouple the forwarding and congestion control planes. We offer a novel architecture for the NDN router in which congestion control and forwarding modules cooperate for interest flow management and congestion control. Based on this framework, we introduce a new explicit feedback-based congestion control protocol (3CP) for managing the consumers' sending rate in an NDN environment that multi-source and multi-path content delivery is intrinsically supported. 3CP employs a new per-packet feedback computation to inform consumers from the available resource of paths toward repositories. Also, it provides feedback to the forwarding mechanism of a router for adjusting the sending rate of interest packets to each interface. By interest flow management, 3CP controls the traffic of data packets in the network. As a significant achievement, 3CP prevents multi-path flows from acquiring more network resources and could manage fair resource allocation to the flows in each path, whereas the consumers obtain the same throughput. The packet-level simulation was conducted by an NDN simulator, and the results confirmed that 3CP outperforms the existing multi-source/multi-path congestion control mechanisms in NDN. © 2004-2012 IEEE.
Publication Date: 2021
Wireless Personal Communications (09296212) 119(2)pp. 1541-1575
Unmanned Aerial Vehicles (UAVs) are well-developed technologies that were first utilized for military applications such as border monitoring and reconnaissance in hostile territories. With the advancement of the Internet of Things (IoT) systems and smart mobile devices, several applications in various industrial, agricultural, smart homes, smart cities, smart transportation, etc. domains have emerged. These applications usually require broad coverage, high energy consumption, computation-intensive processing, and access to rich data gathered by sensor devices. UAVs’ inherent features such as high dynamicity, low deployment and operational costs, quick deployment, and line of sight communication have motivated researchers in the IoT domain to consider UAVs integration into IoT systems toward the notion of UAV-assisted IoT systems. In this paper, recent literature on UAV-assisted services in IoT environments is studied. A service-oriented classification is applied in order to categorize the presented schemes into four broad domains of UAV-assisted data-related services, UAV-assisted battery charging, UAV-assisted communications, and UAV-assisted Mobile Edge Computing (MEC). The literature belonging to each category is summarized with respect to their main points. Finally, some possible future directions are discussed to highlight the challenges associated with designing UAV-assisted IoT systems. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.
The considerable growth of the number of networked devices in the world has led to the development of various and new programs in the field of IoT, which are often limited to the current network infrastructure, on the other hand, force the network administrator to implement complex network policies manually. Due to this congestion of equipment as well as the increasing complexity of traditional network configuration, Software-Defined Networks (SDNs) facilitate network management by separating the control and data layers and creating network rules. For these facilities, these networks appear to be a good infrastructure for IoT networks will enable network programming to develop new and more efficient services to meet real needs. In addition, the variety of IoT equipment can increase complex and inconsistent network rules in SDN-based switches, making network management difficult. Accordingly, in this paper, we will try to model the behavior of anomaly rules distributed in software-defined networks that have been created by different apps in the Internet of Things. It can identify their relationship with other rules in the network and avoid registering them. © 2021 IEEE.
One of the attacks in the RPL protocol is the Clone ID attack, that the attacker clones the node's ID in the network. In this research, a Clone ID detection system is designed for the Internet of Things (IoT), implemented in Contiki operating system, and evaluated using the Cooja emulator. Our evaluation shows that the proposed method has desirable performance in terms of energy consumption overhead, true positive rate, and detection speed. The overhead cost of the proposed method is low enough that it can be deployed in limited-resource nodes. The proposed method in each node has two phases, which are the steps of gathering information and attack detection. In the proposed scheme, each node detects this type of attack using control packets received from its neighbors and their information such as IP, rank, Path ETX, and RSSI, as well as the use of a routing table. The design of this system will contribute to the security of the IoT network. © 2021 IEEE.
Publication Date: 0
pp. 99-105
Industry 4.0 provides a framework for applying new technologies in industrial environments to boost the efficiency and intelligence. A recently blossomed technology in Industry 4.0 is Internet of Things (IoT), which allows us to create a smart environment by connecting various equipment. One of the main applications of IoT in a smart factory is to design monitoring systems, which helps put the behavior of devices under permanent and comprehensive supervision. However, the rapid growth and change in the monitoring facilities creates a big challenge for people who either want to use that equipment in Industry 4.0, or want to update the systems to benefit from this technology. To address this problem, this paper presents new approach based on model-driven engineering paradigm, for simplifying the design and development of real-Time monitoring systems in an industrial environment. Our approach includes a domain-specific modeling language, a graphical editor, and model-To-code transformations that generate a hardware descriptive code, a mobile application, and a web application for a monitoring system. To evaluate the applicability of our approach, a scenario in the power industry has been designed, which offers user a VHDL code, a mobile application, and a web application for monitoring processes of the plant. © 2020 IEEE.
Publication Date: 0
pp. 33-38
Information-Centric Networking (ICN) is focused on content itself as the key factor of communication instead of network addresses. As a successful nominee for future architecture on the Internet, ICN provides a networking paradigm shift from host-oriented to content-oriented communication. This means that a user can declare its desired content by the unique name of that content irrespective of the hosting location. ICN provides high performance content distribution framework, stronger security solutions, better mobility support and scalable network architecture. It supports different naming schemes encompassing flat, hierarchical, hybrid, and attribute-value names. These properties construct ICN as an appropriate networking infrastructure for IoT applications such as smart city. ICN can better handle large IoT name spaces with lower processing resource usage. It reduces energy consumption by in-network caching of contents. Considering an NDN-based smart city, the available naming schemes can be classified into hybrid and hierarchical names. The disadvantages of the proposed naming schemes can be summarized as the long length of the names in hierarchical approach, the difficulty of finding unique content in attributed-value naming scheme, not being user-friendly in flat naming method, and complexity in hybrid naming structures. Considering these drawbacks, we presented a hybrid name scheme for the smart city by PURSUIT architecture that provides faster name lookup in IoT communications. © 2020 IEEE.
Yazdinejad, A. ,
Parizi, R.M. ,
Bohlooli, A. ,
Dehghantanha, A. ,
Choo, K.R. Publication Date: 2020
Journal of Network and Computer Applications (10848045) 156
The emergence of new network technologies and users' ever-increasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the high-level P4 language is applied to allow the description of its register-transfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through pre-processing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320 MHz clock speed, which in comparison with NetFPGA-10G, NetFPGA-SUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex-7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flip-flops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures. © 2020 Elsevier Ltd
Publication Date: 2017
International Journal of Engineering, Transactions B: Applications (1728144X) 30(11)pp. 1714-1722
Software Defined Network (SDN) is a new architecture for network management and its main concept is centralizing network management in the network control level that has an overview of the network and determines the forwarding rules for switches and routers (the data level). Although this centralized control is the main advantage of SDN, it is also a single point of failure. If this main control is made unreachable for any reason, the architecture of the network is crashed. A distributed denial of service (DDoS) attack is a threat for the SDN controller which can make it unreachable. In the previous researches in DDoS detection in SDN, not enough work has been done on improvement of accuracy in detection. The proposed solution of this research can detect DDoS attack on SDN controller with a noticeable accuracy and prevents serious damage to the controller. For this purpose, fast entropy of each flow is computed at certain time intervals. Then, by the use of adaptive threshold, the possibility of a DDoS attack is investigated. In order to achieve more accuracy, another method, computing flow initiation rate, is used alongside. After observation of the results of this two methods, according to the described conditions, the existence of an attack is confirmed or rejected, or this decision is made at the next step of the algorithm, with further study of flow statistics of network switches by the perceptron neural network. The evaluation results show that the proposed algorithm has been able to make a significant improvement in detection rate and a reduction in false alarm rate compared to closest previous work, besides maintaining the average detection time on an acceptable level.
Publication Date: 0
pp. 83-121
Wireless applications have become significant in numerous fields [1] such as the auto industry. Indeed, the convergence of telecommunication, computation, wireless technology, and transportation technologies has contributed to the facilitation of our roads and highways as far as communications are concerned. This convergence in a sense is considered as a platform in intelligent transportation systems (ITS) where each vehicle is assumed to be equipped with devices as nodes in order to create contact with other nodes. Mobile ad hoc networks (MANETs) were introduced in Chapter 3. Because the features of a vehicle network are different from those of other types of MANETs, this network is called a vehicular ad hoc network (VANET) [2]. © 2017 by Taylor & Francis Group, LLC.
Publication Date: 2016
Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A (02533839) 39(4)pp. 493-497
Wireless sensor networks (WSNs) consist of small nodes that are capable of sensing, computing, and communication. One of the greatest challenges in WSNs is the limitation of energy resources in nodes. This limitation applies to all of the protocols and algorithms that are used in these networks. Routing protocols in these networks should be designed considering this limitation. Many papers have been published examining low energy consumption networks. One of the techniques that has been used in this context is cross-layering. In this technique, to reduce the energy consumption, layers are not independent but they are related to each other and exchange information with each other. In this paper, a cross-layer design is presented to reduce the energy consumption in WSNs. In this design, the communication between the network layer and medium access layer has been established to help the control of efforts to access the line to reduce the number of failed attempts. In order to evaluate our proposed design, we used the NS2 software for simulation. Then, we compared our method with a cross-layer design based on an Ad-hoc On-demand Distance Vector routing algorithm. Simulation results show that our proposed idea reduces energy consumption and it also improves the packet delivery ratio and decreases the end-to-end delay in WSNs. © 2016 The Chinese Institute of Engineers.
Publication Date: 0
pp. 268-272
Nowadays, Multi-hop wireless networks have achieved lots of attention due to their ease of development, low cost, and other advantages. Wireless channels have broadcast nature, and a sent packet can be heard by the nodes in the sender's transmission range. This feature is used in opportunistic routing to forward the packets and to enhance the network efficiency. In most of the opportunistic routing algorithms, forwarder nodes are pre-selected by the source nodes. Forwarders should be coordinated for the packet forwarding and one of them is finally selected as the next hop. If the forwarder list is large, coordination's computational overhead will be high. A new Energy efficient opportunistic routing algorithm, named EOpR is presented in this paper that selects the candidate nodes on the packets' fly. This selection is based on the region and the nodes' residual energy. Candidate nodes set a timer and the one whose timer expires first is selected as the next hop. Simulation results showed higher network performance in the terms of network's lifetime and also throughput compared to ROMER. The number of duplicate packets also decreases in EOpR. © 2015 IEEE.
Publication Date: 2015
Ad Hoc Networks (15708705) 25(PB)pp. 472-479
Opportunistic routing is a promising routing paradigm that achieves high throughput by utilizing the broadcast nature of wireless media. It is especially useful for wireless mesh networks due to their static topology. In the current opportunistic routing protocols, it is assumed that all nodes have enough incentive and resource to help the source regardless of their load and presence of other network flows. In addition, the effect of each active flow on other flows and network status is reflected latter by means of a link quality metric (e.g. ETX) which is updated periodically. The coarse-grained behavior of the metric is not in harmony with network flows dynamics. Therefore, some flows may undergo performance degradation between two consecutive periodic updates of the metric. Our proposed approach which is called Dynamic Cooperative Routing (DCR) modifies MORE and equips it with an adaptive decision making mechanism. We use learning automata to accommodate network dynamics when building an opportunistic path for a flow. The learning automata are activated whenever the source transmits a new data batch for the flow. We have shown through simulation that DCR outperforms MORE when two or more flows are active simultaneously and in the presence of background unicast traffic. © 2014 Elsevier B.V. All rights reserved.
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