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Electronics (Switzerland) (20799292) 13(7)
Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V. © 2024 by the authors.
Mahboob sardroudi, F. ,
Habibi M. ,
Moaiyeri, M.H. ,
Mahboob sardroudi, F. ,
Habibi, M. ,
Moaiyeri, M.H. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025
Recently, approximate computing and dynamic logic design techniques have been shown to be effective for energy consumption reduction in the design of CNFET -based ternary arithmetic circuits, such as ternary half adders, 1-trit multipliers, and full adders. In this paper, the use of such a design strategy is studied in order to design other large computational blocks. Due to the long delay paths in these large computational circuits, further modifications in the logic can enhance the performance in some scenarios. Subsequently, a dynamic ternary approach is presented, which can break the pass transistor path and improve the performance in long delay chains. The proposed circuit designs of an approximate dynamic ternary full adder and a 4:2 dynamic ternary compressor work correctly under various supply voltages, temperatures, and fan outs. HSpice simulations using the 32 nm Stanford CNFET model, also show a 10% to 85% reduction in energy usage or PDP and 24% to 86% improvement in terms of EDP, respectively compared to previous methods. The proposed circuits NED, MED, PSNR, and SSIM in image multiplication have also been acceptable regarding previous research. © 2024 IEEE.
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS (00989886) 53pp. 1234-1252
Nanopore ion channels are a promising solution for certain molecular structure analyses. Large arrays of nanopore channels and their associated readout circuits are used in many molecular studies such as DNA sequencing. Readout circuits must meet challenging performance criteria such as low noise operation, low power consumption, in-channel digitization capability, and high linearity. Previously, sigma-delta modulators have been presented to address these criteria; however, their specifications show drifts with temperature. In this paper, an approach is presented to keep modulator performance constant with temperature variations. For this purpose, the sigma-delta modulator's feedforward and feedback branches are modified so that their gain coefficient remains constant over a certain temperature range. With large sensors arrays, solutions employing high bias currents in the feedback paths are not suitable due to power consumption limitations. Here, the design gives the possibility of switching low current levels in the feedback paths without affecting the ENOB. The proposed temperature compensation solution shows good performance when temperature is swept from 27 degrees C to 100 degrees C. Over the mentioned temperature range, the gain and bandwidth of the modulator show a change of less than 0.4%. It is further shown that for a 10 kHz input current signal with an amplitude of 600 pA, the ENOB and power consumption are 12.9 and 4.6 mW, respectively. In the proposed second-order sigma-delta modulator, the feedforward (voltage-to-current converter) and feedback paths are modified so that the transfer function remains independent of temperature. Over a temperature range of 27 degrees C to 100 degrees C, the gain and bandwidth of the modulator show a change of less than 0.4%. image
AEU - International Journal of Electronics and Communications (16180399) 187
New generation DNA sequencers use an array of electrochemical cells equipped with nanopores, which produce pico-ampere current levels. Due to the large number of channels, low current levels and bandwidths in the order of a few kHz, in the design of these readout circuits, 2D arrays of in-channel, low noise and low power analog to digital converters are preferred. Previously many different sigma-delta modulators have been presented to convert the nanopore current signal into a digital code. Conventionally, the opamps required in these converters will eventually increase the power dissipation of each channel. In this paper a novel Gm-C filter based second order sigma-delta converter is proposed. In the given design, rather than relying on multiple opamps to achieve the necessary gain and noise performance, only a 4 transistor Gm block is used. Evaluations show that while the input referred noise remains close to previous methods, the power dissipation is considerably reduced. A prototype is also implemented to show the effectiveness of the approach. In a 180-nm design, an ENOB of 12.16 bits, RMS input referred noise of 0.2 pA at 10 kHz bandwidth and power dissipation of 8.27 μW is obtained per channel. © 2024 Elsevier GmbH
Shahpari, Nima ,
Rabbani, Payam ,
Malcovati, Piero ,
De La Rosa, Jose M. M. ,
Shahpari n., N. ,
Habibi, M. ,
Malcovati p., ,
De La Rosa J.M. IEEE Access (21693536) 11pp. 67113-67125
The input capacitance of the SAR ADC is considered a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance is proposed. The ADC is based on a separated DAC and sample-and-hold blocks (SB) structure. The SB structure suffers from variation in the input common-mode voltage of the comparator, leading to nonlinear input-referred offset and kickback noise. Here, a closed-loop low-power rail-to-rail offset cancellation technique for the comparator, based on body voltage tuning, is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 mu V and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input of the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch's controlling signal is also modified to achieve less than 1 LSB error and 18.9% lower power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and the input capacitance is reduced to 2 pF, which leads to power consumption of 41 nW in the input voltage supply. Electrical simulations including PVT, MonteCarlo, and post-layout parasitic extraction were conducted to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and a sampling rate of 1 MHz with a power consumption of 117.9 mu W including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.
Electrical Engineering (9487921) 105(3)pp. 1413-1430
In this paper, an interface circuit for far-distance energy harvesting from magnetic field of overhead lines is presented. Due to the specific conditions of this type of energy harvesting, such as low available power, low induced voltage in the energy harvester coil, and change of energy harvester impedance, a direct AC/DC switching converter should be used. A maximum power point tracking solution is also necessary to guarantee impedance matching at different operation points. Since the harvested power is in the range of a hundred micro-watts, the power usage of the control circuitry is of significant importance and conventional design approaches based on microcontrollers and FPGAs which require ADCs, DACs and digital signal processing cannot be applied here. The proposed processing circuitry presented in this paper uses three feedback loops to perform the harvesting and energy transfer control. Only low-power comparators and basic digital gates are used as signal-processing elements to limit the power dissipation of the designed control blocks. The impedance matching inner loop samples the H-bridge voltage drop to extract the output load current and perform PWM impedance matching while transferring a rectified current to the output capacitor. Another inner feedback loop is used at the output capacitor using two-level comparison to regulate the output voltage. For maximum power point tracking an outer feedback loop samples the output voltage transfer rate and using a 50 Hz reference generator, adjusts the parameters of the impedance matching circuit of the first inner loop. With the proposed approach, in addition to converting the AC input power to a DC voltage, the output load is regulated at a fixed potential and using the MPPT control loop, the maximum power available from the coil is delivered to the output with relatively low dissipation. The proposed circuit is evaluated using a 0.18 μm standard CMOS technology and operates as a self-powered circuit without an external power source. Based on the obtained results, the efficiency of the proposed circuit at 119 µW input power is about 92.4%, and the MPPT efficiency is about 95%, which is suitable for low-power applications. © 2023, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.
International Journal of Circuit Theory and Applications (1097007X) 51(6)pp. 2638-2653
In this paper, a new ultra-low-power voltage reference based on a two-stage, all-pMOS topology operating in the subthreshold region is proposed to uniquely meet the pW-power range power consumption requirements of emerging Internet-of-Things applications without significantly compromising the temperature coefficient (TC) and the line sensitivity (LS) performance. The proposed circuit consists of the LS regulator, TC corrector, and TC trimming sections. Based on post-layout Monte Carlo simulations in 180-nm CMOS, the proposed circuit operates with 0.8- to 2.4-V supply potential and generates a reference voltage of 206 mV with a process spread of 7.8%, achieving an average calibrated TC of 4.4 ppm/°C in the temperature range of −20°C to 80°C, and an average LS of 51.5 ppm/V with a power consumption of 25.9 pW at 25°C (469.1 pW at 80°C). © 2023 John Wiley & Sons Ltd.
Electrical Engineering (14320487) 104(5)pp. 3361-3380
Energy harvesting from the magnetic field around overhead power lines is an effective approach to supply power for sensor nodes used for measuring weather conditions and power line monitoring. Due to the low intensity of the magnetic field at far distances from the overhead line, the power extracted by the energy harvester coil in this method is low and in the order of a few hundred μWs. Thus, it is necessary to use interface circuits including AC-DC voltage converters and power management circuits with low power consumption and high efficiency. In this paper, a rectifier-less single stage AC-DC voltage converter is used to convert the alternating magnetic field to a DC voltage, as well as providing matching conditions to transfer maximum power. In the proposed structure, a low power impedance matching PWM generator is presented which uses pulse width domain signal processing, and thus reduces power consumption. The performance of the proposed circuit is demonstrated using theoretical elaborations. In addition, the proposed structure is simulated using a 0.18 μm standard CMOS technology, based on which the circuit power dissipation is about 7 μW at 70 kHz and the proposed circuit efficiency is about 94.5%. The maximum power transferring efficiency is about 96% at 120 µW input power. © 2022, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.
Shahpari, Nima ,
Rabbani, Payam ,
Malcovati, Piero ,
Shahpari n., N. ,
Habibi, M. ,
Malcovati p., ,
De La Rosa J.M. Proceedings - IEEE International Symposium on Circuits and Systems (02714310) 2022pp. 2640-2644
A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits a structure with separate sample & hold and DAC blocks, separated block SAR, to achieve low-input capacitance. In this structure, the comparator input common-mode voltage is variable and, therefore, a rail-to-rail comparator with rail-to-rail offset cancellation is proposed to cancel the input common-mode dependent offset. The proposed comparator is modified to overcome the uneven distribution of kickback noise too. In order to achieve a 12-bit resolution, the bootstrapped switch is modified. With the aid of the proposed offset cancellation, kickback noise reduction, and switch, the ADC achieves 11.08bit ENOB and the input capacitance is reduced to 2 pF, leading to relatively low input power consumption with no need for a reference supply voltage.
International Journal of Electronics (13623060) 109(10)pp. 1645-1660
In energy harnessing applications there are instances where energy should be transferred from a low-power, low-leakage backup battery to a temporary power delivery output capacitor. The high power delivery feature of the storage capacitor usually comes at the price of higher leakage current and thus it cannot replace the long-term energy storage backup battery. This paper presents a CMOS capacitor charger circuit which connects a long term low power battery to a short-burst high power delivery capacitor. The proposed circuit uses a switching output stage with an external inductor to reduce the dissipation during the capacitor charge-up cycle. A sigma-delta modulation approach is used to control the power switches. Under low power transfer scenarios which perform transfer in a longer duration, the proposed approach shows better performance compared with previously presented techniques. It is shown that under different transfer durations the control section only consumes 970nWs. The efficiency of the proposed circuit is more than 90% for average input powers in the 0.7 mW to 2 mW range. © 2021 Informa UK Limited, trading as Taylor & Francis Group.
AEU - International Journal of Electronics and Communications (16180399) 140
Sensor nodes and IoT systems require blocks that not only consume low power but also have good accuracy. Voltage reference generators are also considered important building blocks in sensor interface circuits. This paper presents a solution to increase the accuracy of low power subthreshold voltage generators by lowering the circuit sensitivity to temperature and supply voltage variations. The enhancement is achieved by using two separate stages for temperature coefficient (TC) and line sensitivity (LS) correction. A 0.18 µm standard CMOS process has been used for the proposed structure. The effects of parameter variations in the fabrication process are investigated using post-layout simulation and Monte Carlo analysis. In the supply voltage of 0.4–2 V, an LS of 143.8 ppm/V is obtained. In typical corner conditions, the achieved TC is 7.45 ppm/°C over the temperature range of 0–80 °C. Due to process changes, and mainly affected by threshold voltage variations, the average TC can change to 39.2 ppm/°C. The minimum power consumption at 0 °C and at a supply voltage of 0.4 V is 3.25 pW while the power consumption increases to 2.84 nW in 80 °C and at the maximum supply voltage of 2 V. © 2021 Elsevier GmbH
AEU - International Journal of Electronics and Communications (16180399) 131
Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as equal mobility of electrons and holes, the ability to adjust the threshold voltage by changing the nanotube's diameter, and lower leakage power. In this paper, a dynamic ternary full adder is presented using CNFETs. Subsequently, a 5-trit ripple carry adder is designed based on the proposed dynamic ternary full adder and buffer circuits. The proposed hybrid circuits are designed using clocked dynamic logic. Synopsys HSPICE simulator and Stanford's 32-nanometer CNFET model are used to simulate the circuits. The performance of the approach is evaluated under different supply voltages, loads, and temperatures. It is shown that the proposed full adder has lower power consumption, transistor count, PDP, and EDP compared with previously presented ternary adders. Furthermore, the proposed circuit is more robust to process variations. © 2021 Elsevier GmbH
Dawji, Y. ,
Habibi, M. ,
Ghafar-zadeh, E. ,
Magierowski, S. IEEE Access (21693536) 9pp. 155543-155554
This paper introduces a high-speed mixed-signal readout array in 130-nm CMOS for the amplification and digitization of picoampere-range signals. Its design is inspired by the needs of emerging DNA sequencing technologies based on biological nanopore sensors. To overcome switching and substrate noise this system adopts an in-pixel analog-to-digital converter (ADC) architecture and a novel readout technique while consuming 10x less power than similar designs described in the literature. The in-pixel ADC architecture is inherently scalable and immune to electrical interference which can be extended to 100s of channels. With a 5 pF input capacitance, the amplifiers achieve a maximum bandwidth of 100 kHz and demonstrate a noise floor as low as 4 fA√ Hz and a gain in the range of GΩ at 10 kHz. Circuit noise behaviour and theoretical maximum performance estimates using behavioural models are also discussed. © 2013 IEEE.
Flexible and Printed Electronics (20588585) 6(4)
The developments and advances achieved in organic semiconductors have promised lower costs for integrated circuit production and also fabrication of electronic circuits using printed technology on unconventional substrates such as plastic, clothing, and even skin. An important building block essential to most electronic circuits is a voltage, process, and temperature independent potential generator which can be used to bias amplifiers and produce a fixed reference for sensor devices. The generation of a voltage reference is also important for voltage regulators. Currently, most reported organic integrated circuits use only p-type OFETs in their circuits due to simpler fabrication procedures. Furthermore, air stable p-type organic semiconductors such as pentacene and CuPc are well characterized. In this paper, a low power two stage all PMOS voltage reference generator is proposed. Since properties such as threshold voltage value and device aging are dependent on the OFET structure, the type of device chosen for this purpose will have a direct impact on the circuit performance. Three different types of OFETs with silver, copper, and gold drain/source electrodes are studied in this work. Performance factors such as line sensitivity (LS), temperature coefficient (TC), power consumption, time constant, and output drifts of the fabricated integrated circuits are measured and reported to verify the characteristics of the proposed circuits. It is shown that the drain/source metal choice affects the threshold voltage dependent output potential of the reference generators. © 2021 IOP Publishing Ltd.
MICROELECTRONICS JOURNAL (00262692) 113
This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP. © 2021 Elsevier Ltd
Habibi, M. ,
Dawji, Y. ,
Ghafar-zadeh, E. ,
Magierowski, S. Sensor Review (02602288) 41(3)pp. 292-310
Purpose: Nanopore-based molecular sensing and measurement, specifically DNA sequencing, is advancing at a fast pace. Some embodiments have matured from coarse particle counters to enabling full human genome assembly. This evolution has been powered not only by improvements in the sensors themselves, but also in the assisting microelectronic CMOS readout circuitry closely interfaced to them. In this light, this paper aims to review established and emerging nanopore-based sensing modalities considered for DNA sequencing and CMOS microelectronic methods currently being used. Design/methodology/approach: Readout and amplifier circuits, which are potentially appropriate for conditioning and conversion of nanopore signals for downstream processing, are studied. Furthermore, arrayed CMOS readout implementations are focused on and the relevant status of the nanopore sensor technology is reviewed as well. Findings: Ion channel nanopore devices have unique properties compared with other electrochemical cells. Currently biological nanopores are the only variants reported which can be used for actual DNA sequencing. The translocation rate of DNA through such pores, the current range at which these cells operate on and the cell capacitance effect, all impose the necessity of using low-noise circuits in the process of signal detection. The requirement of using in-pixel low-noise circuits in turn tends to impose challenges in the implementation of large size arrays. Originality/value: The study presents an overview on the readout circuits used for signal acquisition in electrochemical cell arrays and investigates the specific requirements necessary for implementation of nanopore-type electrochemical cell amplifiers and their associated readout electronics. © 2021, Emerald Publishing Limited.
Sensor Review (02602288) 40(4)pp. 521-528
Purpose: The purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement. Design/methodology/approach: In this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number. Findings: The performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented. Originality/value: The presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values. © 2020, Emerald Publishing Limited.
AEU - International Journal of Electronics and Communications (16180399) 118
Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18 µm CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47 µW while operating at 500 MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620 µV. © 2020 Elsevier GmbH
IEEE Transactions on Instrumentation and Measurement (00189456) 69(9)pp. 6613-6620
Low-power wireless stand-alone sensors that can operate without any wiring have received significant attention in sensor network applications. These devices harvest environmental energy resources to supply their power and transfer their collected data using wireless RF links. In many instances, the power supplied from the environment is far less than the power required by the sensor device. In this case, the main solution is to accumulate energy on a storage element, and when enough energy is stored, the sensor node is instantaneously activated using an undervoltage lockout (UVLO) circuit. During this short time burst, the sensor performs the required acquisition, transmits the results, and enters a sleep mode until again enough energy is collected. The quiescent current of the UVLO is the main factor that determines the minimum power level at which the sensor node is still operational. Most wake-up circuits used in conventional devices suffer from a quiescent current of a few hundred nanoamperes. In this article, using a zero-bias-current MOSFET-based approach, a new wake-up circuitry is presented, which lowers the quiescent current down to the picoampere range. As a practical application, the effectiveness of the proposed circuit is shown in the soil moisture monitoring sensor setup. © 1963-2012 IEEE.
Analog Integrated Circuits and Signal Processing (09251030) 99(2)pp. 393-402
Sensor network architectures have gained significant attention in acquiring data over widespread areas. To avoid wiring and power complexities, self-powered operation is desirable in these sensors. For this purpose, low voltage and low power characteristics of the internal electronic building blocks is of significant importance. Since sensor architectures usually require voltage reference circuitry, in this paper, a low voltage, low power bandgap reference circuit block is presented. Using a new two stage topology, the line sensitivity is reduced to a significantly low value of 0.28%/V over a wider power supply range of 0.2 V to 2 V. Due to the use of MOSFETs in the subthreshold region, low voltage and low power operation of about 41 pW at 0.2 V is obtained. Furthermore by introducing a novel cross coupled architecture, the temperature coefficient is enhanced considerably. An average temperature coefficient of 247 ppm/°C is obtained at different corners. The performance of the architecture is studied in a 0.18 µm process using post layout and Monte Carlo evaluations. The evaluation results show improvements in both line sensitivity and temperature coefficients compared with previous work. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.
IEEE Transactions on Instrumentation and Measurement (00189456) 67(9)pp. 2247-2255
Power usage reduction and efficiency enhancement of measurement devices are a major challenge in self-powered wireless sensor nodes and also sensors implanted in the human body. Such instruments should be usually operated using the limited environmental energy resources. Electrochemical sensors and potentiostats are extensively used in this context for the measurement of chemical components. In these cases, a lot of research has focused on internal processing blocks power reduction of the potentiostat circuit. In this paper, a discrete current mode (DCM) switching potentiostat is presented, which can significantly reduce the static power usage at the output stage of the potentiostat compared with linear output stage counterparts. Using time-domain analyses, the unexpected oscillatory behavior of a continuous current mode (CCM) output stage switching potentiostat is investigated. Consecutively, it is shown that in current fabrication processes, this configuration will consume more power than the DCM topology. The correctness of the designs and analyses are shown using both simulation and experimental results. The simulated 0.18- μm CMOS DCM output stage potentiostat has an efficiency of 95% at an output load of 12μA , while the long-channel MOSFET-based prototype implementation shows an efficiency of 64%. © 1963-2012 IEEE.
Journal of Circuits, Systems and Computers (17936454) 27(2)
Smart image sensors with low data rate output are well fitted for security and surveillance tasks, since at lower data rates, power consumption is reduced and the image sensor can be operated with limited energy resources such as solar panels. In this paper, a new data transfer scheme is presented to reduce the data rate of the pixels which have undergone value change. Although different pixel difference detecting architectures have been previously reported but it is shown that the given method is more effective in terms of power dissipation and data transfer rate reduction. The proposed architecture is evaluated as a 100×160-pixel sensor in a standard CMOS technology and comparison with other data transfer approaches is performed in the same process and configuration. © 2018 World Scientific Publishing Company.
International Journal of Circuit Theory and Applications (1097007X) 46(11)pp. 1968-1984
Low-voltage high-precision comparators are the main building blocks of many low-power mixed-mode electronic devices. In this paper, a rail-to-rail high-precision comparator is introduced. The proposed comparator uses 2 parallel input P-type metal-oxide-semiconductor pairs with a dynamic level shifter to ensure rail-to-rail operation. Moreover, the proposed circuit incorporates a rail-to-rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk-tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail-to-rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180 nm complementary metal-oxide-semiconductor technology, and the results proved the rail-to-rail comparison ability in addition to the rail-to-rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non–rail-to-rail approach. The maximum clock frequency of the proposed circuit is 833 MHz, which is slightly more than its counterpart at similar operation conditions. © 2018 John Wiley & Sons, Ltd.
Sensor Review (02602288) 37(4)pp. 468-477
Purpose - The purpose of this study is to propose a pulse width based, in-pixel, arbitrary size kernel convolution processor. When image sensors are used in machine vision tasks, large amount of data need to be transferred to the output and fed to a processor. Basic and low-level image processing functions such as kernel convolution is used extensively in the early stages of most machine vision tasks. These low-level functions are usually computationally extensive and if the computation is performed inside every pixel, the burden on the external processor will be greatly reduced. Design/methodology/approach - In the proposed architecture, digital pulse width processing is used to perform kernel convolution on the image sensor data. With this approach, while the photocurrent fluctuations are expressed with changes in the pulse width of an output signal, the small processor incorporated in each pixel receives the output signal of the corresponding pixel and its neighbors and produces a binary coded output result for that specific pixel. The process is commenced in parallel among all pixels of the image sensor. Findings - It is shown that using the proposed architecture, not only kernel convolution can be performed in the digital domain inside smart image sensors but also arbitrary kernel coefficients are obtainable simply by adjusting the sampling frequency at different phases of the processing. Originality/value - Although in-pixel digital kernel convolution has been previously reported however with the presented approach no in-pixel analog to binary coded digital converter is required. Furthermore, arbitrary kernel coefficients and scaling can be deployed in the processing. The given architecture is a suitable choice for smart image sensors which are to be used in high-speed machine vision tasks. © Emerald Publishing Limited.
Sensor Review (02602288) 37(3)pp. 213-222
Purpose - Sensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor network hardware is their limited available energy resource, which makes the low power design of these sensors important. This paper aims to present a low power sensor which can detect sound waveform signatures. Design/methodology/approach - A novel mixed signal hardware is presented to correlate the received sound signal with a specific sound signal template. The architecture uses pulse width modulation and a single bit digital delay line to propagate the input signal over time and analog current multiplier units to perform template matching with low power usage. Findings - The proposed method is evaluated for a chainsaw signature detection application in forest environments, under different supply voltage values, input signal quantization levels and also different template sample points. It is observed that an appropriate combination of these parameters can optimize the power and accuracy of the presented method. Originality/value - The proposed mixed signal architecture allows voltage and power reduction compared with conventional methods. A network of these sensors can be used to detect sound signatures in energy limited environments. Such applications can be found in the detection of chainsaw and gunshot sounds in forests to prevent illegal logging and hunting activities. © 2017 Emerald Publishing Limited.
International Journal of Circuit Theory and Applications (1097007X) 45(6)pp. 790-810
In this paper a low power CMOS potentiostat is presented for energy limited applications such as human implantable sensors. The main focus is on using different techniques to reduce the power consumption at different circuit blocks, especially in the output stage that delivers power to the electrochemical cell. The proposed technique includes the use of a class D amplifier to reduce conduction power dissipation compared with conventional linear methods. Power dissipation has been improved by several other considerations such as elimination of opamp blocks which consume static power, avoiding current sampling stages and using dynamic latched comparators for loop error calculations. Closed loop stability problem and a low power solution to overcome this issue are addressed in the paper. The role of effective parameters such as inductor value, output MOSFET dimensions and clock pulse timing has been investigated and optimization considerations are used to achieve the low power potentiostat. Evaluation results show that a 12.96-μW potentiostat with 1.03-μW power dissipation and 89% efficiency is achievable with a linearity of R2 = 0.998. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.
Maryam Noorbakhsh S. ,
Habibi M. ,
Maryam Noorbakhsh S. ,
Habibi, M. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025
This paper presents a smart CMOS image sensor with capability of detecting motion and positioning of moving objects such as robots on the chip. The proposed method is based on in-pixel frame difference extraction and event generation upon threshold level detection. Due to the localization unit of the designed sensor, it is able to detect multiple moving objects, obtain each object's size and position, and ultimately localize them. By simulation of the sensors processing algorithms and behavior in MATLAB software, activity rate of the sensors data lines has been studied. According to the simulations and comparisons with conventional image sensors, reduction of sensors activity rate and consequently power consumption has been observed in the proposed method. © 2016 IEEE.
Habibi, M.H. ,
Mardani, M. ,
Habibi, M. ,
Zendehdel, M. Journal of Materials Science: Materials in Electronics (09574522) 28(4)pp. 3789-3795
Zinc tin oxide (Zn2SnO4, ZTO) nano-structured was prepared by green hydrothermal route for dye-sensitized solar cell. The ZTO was coated on fluorine doped tin oxide glass (fluorine doped tin oxide, FTO glass with surface resistivity of 8–10 Ω/sq) as working electrode by Doctor Blade and spin coating techniques. The ZTO nano-composite was characterized by X-ray diffraction (XRD), fourier transform infrared, field emission scanning electron microscopy, energy dispersive X-ray spectrometry, and UV–Vis diffuse reflectance (DRS) spectroscopy. XRD results of ZTO showed cubic spinel structure of Zn2SnO4. FESEM results showed spherical particles with an average grain size of about 46 nm. The DRS spectra of the ZTO nano-composite showed an optical band gap energy of 3.35 eV, which is relatively lower than that of bare ZnO (3.42 eV). The reduced band gap energy lowered the rate of electron–hole pair recombination and increased the photovoltage (Voc). An enhancement of 60% in photo-voltage (Voc) was observed when nano-composite ZTO was used as working electrode compared to zinc oxide under the illumination of one sun (AM 1.5, 100 mW cm−2). The efficiency of the working electrodes using Zn2SnO4 nano-composite was increased 40% compared to simple zinc oxide. The enhanced photo-voltage (Voc) may be attributed to higher Fermi level of the Zn2SnO4 and reduced band gap. © 2016, Springer Science+Business Media New York.
Sensor Review (02602288) 36(4)pp. 368-376
Purpose - The purpose of this paper is to present a DNA hybridization detection sensor. An inexpensive fabrication procedure was used so that the sensors can be disposed economically after the measurement is completed. Design/methodology/approach - Field effect transistor (FET) devices are used in the proposed structure. The FET device acts as a charge detection element and produces an amplified output current based on surface charge variations. As amplification is performed directly at the sensor frontend, noise sources have less effect on the detected signal, and thus, acceptably low DNA concentrations can be detected with simple external electronics. ZnO nano layers are used as the FET active semiconductor channel. Furthermore, a photobiasing approach is used to adjust the operating point of the proposed FET without the need for an additional gate terminal.Findings - The proposed sensor is evaluated by applying matched and unmatched target DNA fragments on the fabricated sensors with capture probes assembled either directly on the ZnO surface or on a nano-platinum linker layer. It is observed that the presented approach can successfully detect DNA hybridization at the nano mole range with no need for complex laboratory measurement devices. Originality/value - The presented photobiasing approach is effective in the adjustment of the sensor sensitivity and decreases the fabrication complexity of the achieved sensor compared with previous works. © Emerald Group Publishing Limited.
IEEE Transactions on Microwave Theory and Techniques (15579670) 64(11)pp. 3492-3500
In the last decades, several analytical approaches for linear RF modeling and design have been introduced. In general, using these approaches, source and load reflection coefficients are calculated for designing input and output matching networks. This reflection coefficient is set to achieve a specific target such as maximum output power and minimum noise or an intermediate condition. The most common linear design approach is the use of S-parameters. However, S-parameters cannot model the nonlinear behavior of amplifiers. Nonlinear RF systems such as power amplifiers are typically designed using nonlinear models and/or load-pull measurements. Recently, X-parameters have been presented to model nonlinear device behavior. In this paper, a new design approach based on X-parameters has been introduced and will be verified by simulations and experimental results. Also, it will be indicated that this method speeds up the design procedure when compared with the load-pull method. Using this approach, we can calculate the load reflection coefficient at the fundamental frequency for minimizing a specific harmonic output power. Finally, the application of this approach in minimizing a specific harmonic in the output signal and increasing the dynamic range of the amplifier will be investigated. © 2016 IEEE.
International Journal of Tomography and Simulation (discontinued) (23193336) 29(3)pp. 32-47
This paper presents an efficient for emotion recognition under occlusion mode of frontal facial images. The proposed algorithm firstly uses combination of Viola-Jones algorithm with skin color information for pure face detection. Then, in the detected face region, the proposed algorithm extracts an optimized Pyramid Histogram of Oriented Gradient (PHOG) descriptor that includes 4 pyramid levels and 4 bins for histogram. The proposed algorithm finally uses a KNN (K Nearest Neighbor) multi-classifier with Euclidean distance which results in high recognitions rate over large databases. The experiments over the RaFD face database show that the average recognition rate of the proposed algorithm for detecting seven common emotions (happy, sad, disgust, fear, angry, surprise and neutral emotions) is 99.52% for non-occluded condition. Moreover, the average recognition rates of the proposed algorithm on JAFFE and CK+, which are another popular face databases, are more than 94.6% and 99.1%, respectively. Averagely, the proposed algorithm achieves to 97.73% emotion recognition rate on over about 2000 facial images. On the other hand, when only half of face image is considered as the system input, the average recognition rate achieves to more than 88.57%, 85.5%, and 96.7% over RaFD, JAFEE and CK+ face images, respectively. Since the proposed algorithm shows high robustness against 50% occlusion in input face images, this algorithm can be used in occlusion conditions too. © 2016 by CESER PUBLICATIONS.
Microelectronic Engineering (01679317) 131pp. 29-35
In this paper, an oligonucleotide hybridization detection sensor is presented. The sensor uses field effect transistor (FET) devices to sense the surface charge, amplify it and produce a detectable output signal. With the FET device, hybridization can be detected at lower volumes and concentrations. The FET device is based on solution processed ZnO nano layers as the semiconductor channel. Since the design uses a low cost fabrication procedure, the sensors can be disposed economically after successful completion of the measurements. Furthermore the presented ZnO FET device benefits from double gate advantages. The bottom gate is used to provide the required initial bias conduction channel while the top gate is used to modulate the threshold voltage using the surface charge variations. The effect of platinum nano particles on thiolated DNA probe assembly at the sensor surface is also investigated in this paper. The presented concept is evaluated using a probe station instrument. The input-output transfer curve of the FET is extracted for different surface configurations including DNA probe, DNA probe hybridized with a match (complementary) target and DNA probe coated with un-match DNA sequence. It is shown that the hybridization can be identified with threshold voltage shifts of the transfer curve. It is also observed that the nano platinum linkers increase the sensor's sensitivity. © 2014 Elsevier B.V. All rights reserved.
IEEE Sensors Journal (1530437X) 15(11)pp. 6454-6459
Here, a generalized induction coil sensor model (more generalized than other models) has been considered at low frequencies (within 0.1-100 Hz), and the equivalent magnetic field of the coil's thermal noise and the sensor's signal-to-noise ratio (SNR) were calculated theoretically based on the dimensions and geometry of the coil winding and its core. In our suggested theoretical consideration, all involved parameters were considered and optimized without any assumption and constraint, while some authors in their latest reports, have been used some assumptions and constraints in their sensor calculations (such as holding constant the sensor's volume and aspect ratio). Our calculations indicated that the equivalent magnetic field of the thermal noise can be minimized by the coil-to-core weight ratio. Moreover, it was found that the sensor's SNR can be maximized with only a special value of core aspect ratio (length to diameter of core ratio). The obtained theoretical results were evaluated experimentally by fabricating a search coil magnetometer model, using the optimum parameters. The resonance frequency and the parasitic capacitance of the coil were measured. Moreover, the variations of the transfer function of the magnetometer, with respect to frequency, were studied. Thus, it was shown that, at low frequencies, our experimentally measured noise data exhibit better agreement with our suggested theoretical results with respect to the state of the art. © 2001-2012 IEEE.
Signal, Image and Video Processing (18631711) 9(5)pp. 1179-1191
Digital images can suffer from periodic noise, resulting in the appearance of repetitive patterns on the image data and quality degradation. In order to effectively reduce the periodic noise effects, a novel adaptive Gaussian notch filter is proposed in this paper. In the presented method, the frequency regions that correspond to noise are determined by applying a segmentation algorithm on the spectral band of the noisy image using an adaptive threshold. Then, a region growing algorithm tries to determine the bandwidth of each periodic noise component separately. Subsequently, proper Gaussian notch filters are used to decrease the periodic noises only at the contaminated noise frequencies. The proposed filter and some other well-known filters including the frequency domain mean and median filters and also the traditional Gaussian notch filter are compared to evaluate the effectiveness of the approach. The results in different conditions show that the proposed filter gains higher performance both visually and quantitatively with lower computational cost. Furthermore, compared with the other methods, the proposed filter does not need any tuning and parameter adjustments. © 2013, Springer-Verlag London.
2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025 10pp. 1154-1158
A low power potentiostat is presented in this work with the aim of power consumption reduction. The proposed potentiostat has been designed to cover sensor currents in the range of milliamps. Simulation results have been obtained for a typical electrochemical cell using a 180 nm CMOS technology. Low power, low settling time and low ripple of output voltage are the main features of the proposed structure. The suggested architecture is an appropriate choice for ultra low power applications such as implantable biosensors. © 2015 IEEE.
Habibi M. ,
Bafandeh A. ,
Montazerolghaem M.A. ,
Habibi, M. ,
Bafandeh A. ,
Montazerolghaem M.A. Integration (1679260) 47(4)pp. 417-430
The high speed and in-pixel processing of image data in smart vision sensors is an important solution for real time machine vision tasks. Diverse architectures have been presented for array based kernel convolution processing, many of which use analog processing elements to save space. In this paper a digital array based bit serial architecture is presented to perform certain image filtering tasks in the digital domain and hence gain higher accuracies than the analog methods. The presented method benefits from more diverse convolution options such as arbitrary size kernel windows, compared with the digital pulse based approaches. The proposed digital cell structure is compact enough to fit inside an image sensor pixel. When incorporated in a vision chip, resolutions of up to 12 bit accuracy can be obtained in kernel convolution functions with 35×28 μm2 layout area usage per pixel in a 90 nm technology. Still, higher accuracies can be obtained with larger pixels. The power consumption of the approach is approximately 10 nW/pixel at a frame rate of 1 kfps. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Microelectronics Reliability (00262714) 54(2)pp. 475-484
Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misalignments, line width variations and contamination particles. In this paper, initially a method is proposed for separately identifying cluster defects from random ones. Subsequently a hardware repair structure is presented to repair the cluster defects with rectangular window transfer vectors using a range-matching content addressable memory (RM-CAM) and random defects using defect aware triple-modular redundancy (DA-TMR) columns. It is shown that a combination of these two approaches is more effective for repairing defects at higher error rates with an acceptable overhead. The effectiveness of the technique is shown by examining defect recovery results for different fault distribution scenarios. Also the mapping circuit hardware performance parameters are presented for various memory sizes and the speed, power dissipation and overhead factors are reported. © 2013 Elsevier Ltd. All rights reserved.
Moallem, P. ,
Amini, F. ,
Habibi M. ,
Amini, F. ,
Habibi, M. ,
Moallem, P. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025 pp. 256-260
Retinal image is one of the robust and accurate biometrics which can be used to authenticate an individual. Feature matching is a key step for any biometric system and its implementation on hardware structures is often challenging due to the required object based processing. This paper presents an approach for retina tree biometric matching which has the capability to be implemented on a low power and high speed VLSI hardware. The key idea behind the presented method is to extract the Gaussian profile of the retinal feature dataset. The proposed technique is evaluated on the public VARIA retina image database. © 2014 IEEE.
International Journal of Circuit Theory and Applications (1097007X) 42(10)pp. 989-1005
In this paper, a high dynamic range digital pixel sensor (DPS) is presented. Each pixel receives light illumination and converts the intensity level to a digital code. The analog-to-digital conversion is performed in-pixel. The pixel structure incorporates light to pulse signal converter and compact in-pixel dynamic counter to convert the pulse signal to binary coded data. Different variations of the custom design dynamic counters are analyzed in a 0.18 μm technology, and their application in the DPS is investigated. It is shown that due to the limited clock frequency required in the sensor pixel, the dynamic counter can be incorporated as a pulse to binary code converter. Performance specifications such as power consumption, dynamic range and resolution of the presented structure are investigated using a 100×100 pixel sensor. The presented sensor is an effective solution for use in digital field programmable smart image sensors and vision chips since the pixel output is a regular binary code while no global digital counter bus is required. The fill factor of the presented design remains close to that of typical DPSs. Copyright © 2013 John Wiley & Sons, Ltd.
Moallem, P. ,
Shokrani, S. ,
Habibi M. ,
Shokrani, S. ,
Moallem, P. ,
Habibi, M. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025 pp. 215-220
Today Human Computer Interaction (HCI) is one of the most important topics in machine vision and image processing fields. Through features can get beneficial information about the variety of emotions and gestures which are produced by the movements of facial major parts. In this paper we presented the technique of Pyramid Histogram of Oriented Gradient for feature extraction and compare it with gabor filters. Six basic facial expressions plus the neutral pose are considered in the evaluations. The KNN and SVM techniques are used in the classification phase. Unlike most emotion detection approaches that focus on frontal face view this method concentrates on three views of the face and can easily be generalized to other poses and feelings. We have tested our algorithm on the Radboud faces database (RaFD) over three directions of head (frontal, 45 degree to the right and 45 degree to the left). Cohn-Kanade (CK+) and JAFFE are two other databases used in this work. The experiments using the proposed method demonstrate favorable results. In the best condition by using Pyramid Histogram Of Oriented Gradient plus KNN classification, the success rates were 100, 96.7, 98.1, 98.3 and 98.9 % for RaFD (frontal pose), RaFD (45 degree to the right), RaFD (45 degree to the left), JAFFE and CK+ databases respectively. © 2014 IEEE.
Sensor Review (02602288) 34(3)pp. 297-303
Purpose - The purpose of this study is to construct imaging pixels using novel bioactive films. Despite the notable progress in electronic imaging devices, these sensors still cannot compete with biological vision counterparts such as the human eye. Light sensitive biolayers and pigments in living organisms show superior performance in terms of low noise operation and speed. Although photoactive biolayers have been used to construct electronic imaging devices, they are usually hard to develop, and the organisms that produce these active layers have low growth rates.
Habibi, M.H. ,
Karimi, B. ,
Zendehdel, M. ,
Habibi, M. Journal of Industrial and Engineering Chemistry (1226086X) 20(4)pp. 1462-1467
Mixed copper-zinc oxide nanostructures (average size 43nm) were effectively fabricated via co-precipitation route. Field-emission scanning electron microscope (FESEM), powder X-ray diffraction (XRD), fourier-transform infrared spectroscopy (FT-IR) and UV-vis diffuse reflectance spectrum (DRS) were used to characterize the properties of the oxides. At the optimized condition, copper-zinc oxide nanostructures were used for fabrication of working electrodes by doctor blade technique on the fluorine-doped tin oxide (FTO) in dye sensitized solar cells. Their photovoltaic behavior were compared with standard using D35 dye and an electrolyte containing [Co(bpy)3](PF6)2, [Co(pby)3](PF6)3, LiClO4, and 4-tert-butylpyridine (TBP). The ranges of short-circuit current (Jsc) from 0.13 to 0.30 (mA/cm2), open-circuit voltage (Voc) from 0.20 to 0.51V, and fill factor from 0.34 to 0.29 were obtained for the DSSCs made using the working electrodes. A titania blocking layer on the copper-zinc oxide surface improve both the open-circuit voltage (Voc), short-circuit current (Jsc) and the power-conversion efficiency is consequently enhanced by a factor of approximately five. © 2013 The Korean Society of Industrial and Engineering Chemistry.
Habibi, M.H. ,
Habibi, A.H. ,
Zendehdel, M. ,
Habibi, M. Spectrochimica Acta - Part A: Molecular and Biomolecular Spectroscopy (13861425) 110pp. 226-232
This research investigates the performance of a zinc ferrite (ZF) as working electrodes in a dye-sensitized solar cell (DSSC). This ZF working electrode was prepared by sol-gel and thermal decomposition of four different precursors including: zinc acetate dihydrate (Zn(CH3COO) 2×2H2O), ferric nitrate nonahydrate (Fe(NO 3)3×9H2O), iron(III) acetate; Fe(C 2H3O2)3, and zinc nitrate hexahydrate, Zn(NO3)2×6H2O. The effects of annealing temperature and precursors on the structural, morphological, and optical properties were investigated. The field emission scanning electron microscope images (FESEM) and scanning electron microscopy (SEM) show that ZFe films are polycrystalline in nature and homogeneous with densely packed grains. Nanoporous zinc ferrite coatings were prepared by doctor blade technique on the fluorine-doped tin oxide (FTO) and used as working electrodes in DSSC. In all DSSCs, platinized FTO and [Co(bpy)3]2+/3+ in 3-methoxy proponitrile were used as counter electrode and redox mediator system respectively. Comparing the fill factors of four different zinc ferrite nanocomposites, the highest fill factor was for ZnFe2O 4-TBL sample. Cell fabricated with ZnFeA working electrode shows relatively higher Jsc. © 2013 Elsevier B.V. All rights reserved.
Habibi, M.H. ,
Karimi, B. ,
Zendehdel, M. ,
Habibi, M. Spectrochimica Acta - Part A: Molecular and Biomolecular Spectroscopy (13861425) 116pp. 374-380
(Figure Presented) Two kind of CuO-ZnO nanocomposite working electrodes were synthesized by sol-gel technology and applied in dye-sensitized solar cells (DSSCs). Their characteristics were studied by field emission scanning electron microscopy (FESEM), X-ray diffraction (XRD) and UV-Vis diffuse reflectance spectrum (DRS). CuO-ZnO nanocomposite thin films were prepared doctor blade technique on the fluorine-doped tin oxide (FTO) and used as working electrodes in dye sensitized solar cells (DSSC). Their photovoltaic behavior were compared with standard using D35 dye and an electrolyte containing [Co(bpy) 3](PF6)2, [Co(pby)3](PF 6)3, LiClO4, and 4-tert-butylpyridine (TBP). The ranges of short-circuit current (JSC) from 0.18 to 0.21 (mA/cm2), open-circuit voltage (VOC) from 0.24 to 0.55 V, and fill factor from 0.34 to 0.39 were obtained for the DSSCs made using the working electrodes. The efficiency of the working electrodes after the addition of TBL was more than doubled. The light scattering and carrier transport properties of these composites promote the performance of dye-sensitized solar cells (DSSCs). © 2013 Elsevier B.V. All rights reserved.
Pourmeidani, H. ,
Habibi M. ,
Pourmeidani, H. ,
Habibi, M. 2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025
Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misintegration and line width variations. In this paper, we propose a method for identifying cluster defects from random ones. The motivation is to repair the cluster defects using rectangular ranges in a range matching content-addressable memory (RM-CAM) and random defects using triple-modular redundancy (TMR). It is believed a combination of these two approaches is more effective for repairing defects at high error rate with less resource. With the proposed fault repairing technique, defect recovery results are examined for different fault distribution scenarios. Also the mapping circuit structure required for two conceptual 32×32 and 64×64 bit RAMs are presented and their speed, power and transistor count are reported. © 2013 IEEE.
Habibi, M.H. ,
Askari, E. ,
Habibi, M. ,
Zendehdel, M. Spectrochimica Acta - Part A: Molecular and Biomolecular Spectroscopy (13861425) 104pp. 197-202
Zinc zirconate (ZnZrO3) (ZZ), zinc oxide (ZnO) (ZO) and zirconium oxide (ZrO2) (ZRO) nano-particles were synthesized by simple sol-gel method. ZZ, ZO and ZRO nano-particles were characterized by scanning electron microscopy (SEM), X-ray diffraction (XRD) and UV-Vis diffuse reflectance spectrum (DRS). Nanoporous ZZ, ZO and ZRO thin films were prepared doctor blade technique on the fluorine-doped tin oxide (FTO) and used as working electrodes in dye sensitized solar cells (DSSC). Their photovoltaic behavior were compared with standard using D35 dye and an electrolyte containing [Co(bpy)3](PF6)2, [Co(pby)3](PF 6)3, LiClO4, and 4-tert-butylpyridine (TBP). The properties of DSSC have been studied by measuring their short-circuit photocurrent density (Jsc), open-circuit voltage (VOC) and fill factor (ff). The application of ZnZrO3 as working electrode produces a significant improvement in the fill factor (ff) of the dye-sensitized solar cells (ff = 56%) compared to ZnO working electrode (ff = 40%) under the same condition. © 2012 Elsevier B.V. All rights reserved.
IEEE Transactions on Instrumentation and Measurement (00189456) 61(3)pp. 708-718
The correlation image sensor (CIS) is used in a variety of applications which involve the extraction and measurement of low-amplitude-modulated light signals from background interferences. Many applications have been reported on measurement of ac magnetic flux, interferometry, eye gaze tracking, and indirect 3-D imaging using these sensors. In this paper, the performance of different derivatives of the CIS is analyzed, and some modification is applied to the CIS to significantly increase its sensitivity at higher frame rates and reduce its output error. The effect of undesired parameters, such as parasitic capacitances, device mismatches, charge transfers, random noise, and temperature variations, is studied, and modified architectures are proposed to reduce them. The maximum demodulation frequency is also shown to be increased compared to original CIS. The presented designs are compared with previous solutions under similar operating conditions using a 0.35-μm standard CMOS technology. It is shown that the designs can be used to detect lower modulated signal levels over a wider background dynamic range. © 2012 IEEE.
Habibi, M.H. ,
Mikhak, M. ,
Zendehdel, M. ,
Habibi, M. International Journal of Electrochemical Science (14523981) 7(8)pp. 6787-6798
A series of working electrode metal oxide semiconductor nanostructured with zinc titanate, zinc oxide and titanium dioxide were coated on the fluorine-doped tin oxide (FTO) conducting glass as working electrodes in dye sensitized solar cells (DSSC). Zinc titanate (ZT), zinc oxide (ZO) and titanium dioxide (TD) nano-particles were synthesized by sol-gel method and characterized by scanning electron microscopy (SEM), X-ray diffraction (XRD) and UV-vis Diffuse reflectance spectrum (DRS). The influence of ZT, ZO and TD thin films was compared with standard titania cells, using D35 dye and an electrolyte containing [Co(bpy)3](PF6)2, [Co(pby)3](PF6)3, LiClO4, and 4-tert-butylpyridine (TBP). Under the same working conditions, the properties of DSSC have been studied by measuring their short-circuit photocurrent density (Jsc), open-circuit voltage (Voc) fill factor (ff) and conversion efficiency (η). The results showed that the cell made of the ZO particles exhibits the largest value of JSC and VOC among these three samples. The variation trend of VOC is the same as that of JSC, that is, ZO > ZT > ZD. The outcome of this study can be crucial for the preparation of reliable paste in a simple way for its application in DSSC. © 2012 by ESG.
2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025 pp. 197-202
The correlation image sensor (CIS) is an important device for detection of modulated light signals at high frame rates. In this paper a demodulation pixel is presented which increases the sensitivity of the CIS device. The pixel is capable of detecting and demodulating light signals at lower illumination levels compared with the previous designs. Furthermore due to the low number of processing stages the random noise at the output remains close to the kT/C reset and photodiode shot noise. The presented design is compared with previous solutions under similar operating conditions using a 0.35μm standard CMOS technology. It is shown that while the fill factor and power consumption of the design is close to the previous structures, it is able to operate at lower modulated illumination levels and higher dynamic range of background intensities. © 2011 IEEE.
Analog Integrated Circuits and Signal Processing (09251030) 67(3)pp. 339-352
Detection of modulated light signals transmitted by active image markers can be used in object localization tasks and machine vision applications. The asynchronous demodulation pixel is able to detect the signal transmitted by these modulated markers. The modulated marker position in a two-dimensional pixel array can be used to identify the marker location in the field. In this paper the asynchronous demodulation pixel is analyzed and its operation is investigated in the presence of non-ideal effects such as parasitic elements, device mismatches and process variations. The effect of demodulator bias conditions and different switch pulsing techniques are examined and a modified demodulator controlling method is presented to increase the dynamic range and sensitivity of the pixel compared with the common operation schemes. The different demodulator structures are also simulated as 64 × 64 pixel array sensors using a 0.18 μm standard CMOS process and their operation is compared regarding sensitivity, filter transfer function, pixel size and power consumption. © 2010 Springer Science+Business Media, LLC.
International Journal of Circuit Theory and Applications (1097007X) 39(1)pp. 17-30
This paper presents a novel technique for classification and segmentation of a multiple-object image scene. Each object in the scene is tagged by a flashing LED operating at a specific frequency. The vision sensor, based on this technique, demodulates the captured light signal, omits the background illumination, and performs classification by assigning a unique ID-tag to each region based on its flashing light frequency. The process is performed in-pixel by an asynchronous demodulation and frequency identification circuit, which is designed in a standard 0.6μm CMOS technology. Simulation results confirm the validity of the proposed structure. At a frame rate of 250 fps the power consumption is 2.6μW/pixel, which is relatively low compared with those of sensors with similar functionality. The structure is intended for use as a low power, inexpensive solution in robot visual position feedback and localization. © 2009 John Wiley & Sons, Ltd.
2025 29th International Computer Conference, Computer Society of Iran, CSICC 2025
The efficient transmission of video rate data is a demanding need in camera surveillance systems. This paper presents a low power smart CMOS image sensor which is suitable for surveillance applications. The sensor captures the image scene and using in-pixel difference detectors, it detects the temporal change events in the image. To reduce the power consumption, only the portions of the image scene with intensity change are transferred to the output. For this purpose, the performance of two different event driven data transfer methods, pixel based and window based, are investigated and it is shown that each method is appropriate under different surveillance conditions. The performance of the technique is shown using a 64x64 pixel sensor designed in a 0.18 μm standard CMOS technology. The sensor chip consumes 0.5mW of power while operating at 30fps. © 2010 IEEE.
Industrial Robot (17585791) 37(1)pp. 62-69
Purpose - The purpose of this paper is to present a novel image-labeling CMOS sensor for modulated marker detection. Design/methodology/approach - An image scene with multiple objects, each identified by a flashing light-emitting diode (LED), is captured by the sensor. The LED's frequency is a representation of the object ID-tag. The sensor detects and labels the objects by identifying the signal frequencies. The processing is performed in-pixel and, since the object detection task is simplified, power dissipation is reduced. A 64×64 pixel sensor is designed in the 0.6 μm CMOS technology. Findings - Simulation results show successful object identification. At a frame rate of 250 fps the measured power consumption is 11 mW, which is less than those of the previously reported object detection solutions. The application of the presented sensor is shown in several different robotic fields such as unmanned aerial vehicles (UAVs) vision, household robots and industrial robots. It is also explained how the sensor can be used for low-power localization and position detection of the robot vehicles. Originality/value - The paper shows that the sensor is a suitable solution for low-power landmark detection and robot localization. © Emerald Group Publishing Limited.
Samavi s., S. ,
Habibi, M. ,
Shirani s., S. ,
Rowshanbin n., Image and Vision Computing (02628856) 28(11)pp. 1557-1568
Fractal coding algorithm has many applications including image compression. In this paper a classification scheme is presented which allows the hardware implementation of the fractal coder. High speed and low power consumption are the goal of the suggested design. The introduced method is based on binary classification of domain and range blocks. The proposed technique increases the processing speed and reduces the power consumption while the qualities of the reconstructed images are comparable with those of the available software techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. The application of the proposed hardware is shown in image compression. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared with the existing designs. Other applications of the proposed design are feasible in certain fields such as mass-volume database coding and also in video coder's block matching schemes. © 2010 Elsevier B.V. All rights reserved.
International Journal of Distributed Sensor Networks (15501329) 5(6)pp. 675-692
Using a two-dimension array of MOSFET switches, a robust, high speed object tracking CMOS sensor is presented. The edges of the image scene are extracted by the in-pixel differential comparators and a region (object) of interest, which is selected by the user, is segmented using the switch network. Tracking is performed by automatic reselection of the desired region. The proposed design presents less sensitivity to threshold adjustments compared to the binarization technique. The processing is mainly performed in analog domain, thus reducing dynamic power dissipation and making the chip ideal for low power applications. The sensor has been designed as a 50 × 50 pixel VLSI CMOS chip in the 0.6 μm technology. Features such as power dissipation, output latency, and operating frequency are reported. © 2016 Taylor & Francis Group, LLC.
In this paper a modulated light detection smart CMOS image sensor is presented. The design has the ability to sense asynchronous signals transmitted from electronic markers such as flashing light emitting diodes (LEDs) tagged on moving robots. With the presented sensor, object localization and position detection functions are simplified, performed at higher speeds in real time, and power requirement is reduced. The sensor in-pixel processing, filters out the background image data and detects the modulated marker regions. Object localization is facilitated by the use of distributed sensors to cover a more extended space. Since marker locations are extracted locally at each sensor, data transmission rate at each node and power demand is reduced; thus the sensor nodes can be designed as wireless and self powered units. The functionality and power consumption of the proposed design are presented in the 0.35μm standard CMOS technology. ©2009 IEEE.
International Journal of Electronics (13623060) 96(8)pp. 821-836
In this article an object tracking CMOS sensor is presented. The architecture incorporates photo detection devices and pixel level processing elements for capturing and processing the image data and extracting the object's coordinates. The edges of the image scene are extracted by in-pixel edge detectors and the region (object) of interest, selected by the user, is segmented using a switch network. Coordinates of the desired region are obtained by extracting the geometric centre of the region. Tracking of the selected object is then performed by automatic reselection of the region using the updated coordinates. The proposed design presents less sensitivity to threshold adjustments than binarisation techniques. The sensor has been designed as a 6464 pixel VLSI CMOS chip in the 0.35m standard CMOS technology. The proposed structure is analysed with regard to its operation in the presence of mismatches and noise. Features of the sensor are reported and compared with some previous object tracking designs. Because the power dissipation is small, the chip is ideal for low-power applications.
Shahraki, A.S. ,
Nabavi, A. ,
Habibi, M. ,
Bornoosh, B. pp. 955-958
This paper presents the design of a dynamic reconfigurable processor using an array of two dimensional logarithmic numbering system (LNS) processing elements and registers. By programming the processor, the array configures dynamically during operation and executes the required task with different structures in each phase. The proposed coarse grain array architecture is suitable for implementation of software radio baseband equalizers. Since redundant elements found in fine grained structures are reduced, the design consumes less chip area and power. Several different equalizer algorithms including the CMA for QPSK and BPSK signals, the finite interval CMA and the sliding window CMA equalizers are implemented and programmed on the proposed processor array and successive operation is shown. The architecture is designed in a 0.13 μm CMOS technology and simulated for extraction of chip specifications. Power consumption, operation speed, gate count and chip area of the design are reported. © 2007 IEEE.
Achieving the maximum power is the major and important task in the PV applications. Many of Maximum Power Point Tracking, MPPT, methods are developed based on optimal voltage or current factors, which are assumed to be constant. In this paper, a PV system is modeled such that variations of the optimal voltage factor over the environmental conditions are highlighted. An adaptive cascade MPPT controller is proposed to follow the optimal voltage factor in each insolation level, in addition to regulating the output power at its maximum possible value via a boost converter. Simulations are performed to verify the validation of the proposed MPPT system. © 2007 IEEE.
In this paper a low cost implementation of hybrid stepper motor controller and driver is presented. The controller incorporates an inexpensive microcontroller to perform chopper control, current feedback, adaptive ripple torque reduction based on the presented algorithm. The design uses current feedback to compensate torque ripples resulting from both motor structure and pulse commands issued from the higher level system, furthermore no position measurement is needed in the controller design thus position sensors are not required. The controller needs no information on the load torque and motor parameters and is automatically adjusted to position the motor to the desired location with minimum torque ripple. The microcontroller's algorithm abilities and performance is shown using computer simulations on a hybrid stepper motor model with different parameters, speeds and under different load torques. An implementation of the system and practical test results are also presented.
