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Journal of Supercomputing (15730484)80(2)pp. 2067-2127
In Internet-of-Things (IoT)-based healthcare systems, real-time healthcare data are gathered from patients’ sensors with limited resources and transferred to end-users through gateways and healthcare service providers. Privacy of patients is a main challenge of these systems. Although privacy has already been considered in IoT-based healthcare systems, best centralized approaches yet suffer from collusion attack. Therefore, some researchers have come up with blockchain-based solutions to protect patients’ privacy in IoT-based healthcare systems. However, those methods assume that parts of the entities along the end-to-end communication path from patients’ sensors to the end-users are trusted or even assuming no privacy threats from internal attackers. Therefore, there is a lack of a blockchain-based approach in IoT-based healthcare systems to provide privacy for patients, assuming that all system entities are untrusted. To overcome these challenges, in this paper, we leverage a three-layered hierarchical blockchain, the zero-knowledge proof (ZKP), and the ring signature method to achieve data and location privacy of patients against both internal and external attackers. In addition, the proposed method provides anonymous authentication, authorization, and scalability, which are essential features in healthcare systems. Intuitive and formal security analyses demonstrate the resilience of our scheme against various attacks such as denial of service (DoS), modification, mining, storage, and replay attacks. The proposed method is compared to a recent blockchain-based method and also a centralized privacy-preserving scheme. Compared to the similar blockchain-based method, the computational overhead and delay of the authentication and data transfer phase are about 35% and 37% higher, respectively. Instead, the proposed method reduces memory usage of gateways by about 55% and diminishes the computational overhead and delay of information access phase by about 30% and 33% compared to the previous blockchain-based method. Therefore, the proposed method does not increase overhead and end-to-end delay considerably compared to the previous blockchain-based scheme, while some other performance metrics and security features are improved. Moreover, compared to a previous centralized method, the proposed approach shows more than 25% decrease in communication overhead and 22% improvement in memory usage of gateways, in average. Although the use of the blockchain imposes more computational overhead on service providers and may increase the latency compared to the centralized approach (depending on the type of the blockchain technology that is used), these weaknesses are negligible at the expense of increased security. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Journal of Visual Communication and Image Representation (10473203)103
The state of the art steganography approaches strictly assume that the receiver has access to a steganographic key. This limitation was mitigated for images in spacial domain, but the approach does not apply to JPEG images. In this paper, we introduce a keyless steganography scheme for JPEG images. Despite the spatial domain counterpart, our approach for the JPEG domain effectively preserves higher-order statistical models that are used in steganalysis. We show that our approach does not degrade image quality either. The proposed approach is a Side-Information (SI) steganography in the sense that its input is a never-compressed image. Another characteristic of the proposed approach is the separation of the embedding modification and data extraction domains, which can initiate further studies of similar approaches in the future. © 2024
Quantum Information Processing (15700755)(4)
The reversible multipliers are of significant importance in implementing the computational systems by the novel technologies. The generation section of partial products and adders existing in the provided multipliers so far is designed separately. This increases the constituent blocks’ number of the final circuit. As the constituent number of blocks in a circuit increases, the number of inputs and outputs rises. The enhancement of the reversible circuits will be costly in most novel technologies. In this study, a structure is provided for the n× n quantum multipliers, where the number of constituent blocks is significantly declined compared to the existing designs. Also, the number of ancilla inputs and garbage outputs is at the minimum level in each block. In the provided method of this article, each multiplier column has been designed in the form of a block (instead of the multiplier design in two separate steps). Also, a method is provided for making the circuit fault-tolerant. In this case, instead of using the fault-tolerant gates in the multiplier design process, first, the circuit is designed regularly, and ultimately, the fault tolerance is added to it. Accordingly, the number of ancilla inputs and garbage outputs of the regular quantum multiplier is decreased by 66% and 70%, respectively, compared to the previous works. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Electronics (Switzerland) (20799292)(5)
Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods. © 2023 by the authors.
Physical Communication (18744907)
Femtocells are designed to cover small indoor areas. In commercial buildings, femtocell placement and number is one of the most important network issues. In such buildings, another problem is uneven traffic distribution in different spaces, which causes high traffic and low traffic areas. Due to the small coverage areas of femtocells and these high traffic and low traffic areas, some femtocells are overloaded and some femtocells are underloaded. Also, increase in the distance of high-traffic areas from the femtocells, increases the number of resource blocks used. These issues reduce network efficiency. In this article, femtocell placement has been managed in such a way that the traffic load on the femtocells is balanced and is reduced the number of resource blocks used in the building and efficiency is increased. A mathematical model for femtocell placement has been introduced which balancing the femtocell load and reducing the average number of resource blocks used, the conditions of maximum coverage area and minimum femtocell number should also be fulfilled. This challenge has been addressed by using non-dominated sorting genetic algorithm (NSGA-II). An initial population generation algorithm and a selection function are also presented. The assessment results indicate that compared to the latest studies, this newly proposed method reduces the average load on the whole building by 79% and decreases the load variance between the femtocells by 86%. © 2022 Elsevier B.V.
Journal of Supercomputing (09208542)(1)
The design of a reversible multiplier is very important due to its wide range of applications in implementing computing systems using new technologies. In most multipliers presented so far, partial product generators and adders are designed separately. This increases the number of blocks that make up the final circuit. Reversible circuits have to use ancilla inputs and garbage outputs. The more blocks in a circuit, the greater the number of inputs and outputs. In this study, a column-wise structure is designed for the multiplier to reduce the number of individual blocks making it up. Increasing the size of reversible circuits in most new technologies is very costly. The number of blocks of the structure presented in this paper for a reversible multiplier is significantly reduced compared to existing designs. Moreover, the number of ancilla inputs and garbage outputs in each of these blocks is minimized. Therefore, the values of these criteria in the proposed multiplier are much lower than those of the previous works. In the proposed method, instead of designing the multiplier in two separate steps, each multiplier column is designed in the form of a block. Therefore, the number of blocks that make up the circuit is equal to the number of the columns of the multiplication operation. As a result, the number of ancilla inputs and garbage outputs is reduced by up to 66% compared to previous works. This column-wise structure is provided for multiplying two 4-bit numbers; however, it is also scalable for designing larger multipliers. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Journal of Computational Electronics (15698025)(1)
The synthesis of reversible circuits is a challenge on which many studies have been conducted. Different algorithms attempt to propose a more optimal implementation for each description of a reversible circuit, using reversible gates. In this paper, an algorithm is proposed which, by a heuristic method using a Simulated Annealing algorithm, tries to find a near-optimal circuit to the given truth table. Unlike previous methods, this method does not necessarily require a correct initial circuit to improve it. It can start from a correct circuit or a near-correct circuit or even from an empty circuit, and tries to get a circuit that is better than the initial circuit. It can also achieve different circuits in different runs that are better than the initial circuit. Finally, from the various circuits that this algorithm has produced in different runs, the best is selected as the final circuit. The proposed algorithm also tries to produce a circuit as simple as possible with respect to don’t-care combinations. Also, the current algorithm does not depend on the type of gates. Any library, including arbitrary reversible gates, can be used in this method. © 2021, Springer Science+Business Media, LLC, part of Springer Nature.
Transactions on Emerging Telecommunications Technologies (21615748)(9)
The femtocell networks have been developed to solve the indoor coverage issues. In the large commercial buildings, finding the minimum number of femtocells and their locations with a full coverage of the building is a complicated problem. This article attempts to minimize the number of femtocells in a large building while providing maximum coverage. In this article, the locations of the femtocells are determined such that the total number of handovers in the building is minimal. For this purpose, the building area is divided into small and equal-sized subregions, and a femtocell matrix coverage is obtained for each subregion using the path-loss equation. We utilize the femtocell matrix coverage and propose a mathematical model to minimize the number of femtocells with a maximum (almost complete) coverage of the building area. We employ the genetic algorithm to solve this NP-hard problem. An efficient algorithm is also presented to create the initial population for the genetic algorithm. Based on the past behavior of the users, we select the locations for the femtocells to reduce the number of handovers. Numerical results indicate that with almost complete coverage, our proposed method reduces the femtocell counts up to 55% and reduces the number of handovers up to 30% compared with the previous work. © 2021 John Wiley & Sons, Ltd.
The Isc International Journal Of Information Security (20082045)(2)
There are many different ways of securing FPGAs to prevent successful reverse engineering. One of the common forms is obfuscation methods. In this paper, we proposed an approach based on obfuscation to prevent FPGAs from successful reverse engineering and, as a result, hardware trojan horses (HTHs) insertion. Our obfuscation method is using configurable look up tables (CFGLUTs). We suggest to insert CFGLUTs randomly or based on some optional parameters in the design. In this way, some parts of the design are on a secure memory, which contains the bitstream of the CFGLUTs so that the attacker does not have any access to it. We program the CFGLUTs in run-time to complete the bitstream of the FPGA and functionality of the design. If an attacker can reverse engineer the bitstream of the FPGA, he cannot detect the design because some part of it is composed of CFGLUTs, which their bitstream is on a secure memory. The first article uses CFGLUTs for securing FPGAs against HTHs insertion, which are results of reverse engineering. Our methods do not have any power and hardware overhead but 32 clock cycles time overhead. © 2020 ISC. All rights reserved.
Wireless Networks (10220038)27(6)pp. 4009-4037
Preserving patients’ privacy is one of the most important challenges in IoT-based healthcare systems. Although patient privacy has been widely addressed in previous work, there is a lack of a comprehensive end-to-end approach that simultaneously preserves the location and data privacy of patients assuming that system entities are untrusted. Most of the past researches assume that parts of this end-to-end system are trustworthy while privacy may be threatened by insider attacks. In this paper, we propose an end-to-end privacy preserving scheme for the patients assuming that all main entities of the healthcare system (including sensors, gateways, and application providers) are untrusted. The proposed scheme preserves end-to-end privacy against insider threats as well as external attacks concerning the resource restrictions of the sensors. This scheme provides mutual authentication between main entities while preserves patients’ anonymity. Only the allowed users can access the real identity of patients alongside their locations and their healthcare information. Informal security analysis and formal security verification of the proposed protocol in AVISPA show that it is secure against impersonation, replay, modification, and man-in-the-middle attacks. Moreover, performance assessments show that the proposed protocol provides more security services without considerable growth in the computation overhead of the sensors. Also, it is shown that the proposed protocol diminishes the signaling overhead of the sensors and so their energy consumption compared to the literature at the expense of adding a little more signaling overhead to the gateways. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
The Isc International Journal Of Information Security (20082045)(1)
Nowadays the security of the design is so important because of the different available attacks to the system. the main aim of this paper is to improve the security of the circuit design implemented on FPGA device. Two approaches are proposed for this purpose. The first is to fill out empty space using flip-flops and LUTs so that there is no available space for inserting a hardware Trojan. We name this filling structure as Gate-chain. The second approach increases the security of the implemented design by identifying the low observable/controllable points of the main design and wiring them to the unused ports or the pre-designed Gate-chains. The proposed solutions not only prevent Trojan insertion but also increase the Trojan detection capabilities. Simulation results on Xilinx devices implementing different benchmarks show that the proposed method incurs dynamic power overhead just in test mode with less than one percent of delay overhead for critical path in normal mode. © 2020 ISC. All rights reserved.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (03029743)
This paper proposes the use of Evolvable Hardware (EH) architectures as a countermeasure against power analysis attacks. It is inspired by the work of Sasdrich et al., in which the block cipher PRESENT is protected against power analysis attacks through the use of dynamic logic FPGA reconfiguration. The countermeasure consists of splitting the substitution boxes (S-boxes) into two parts with a register in between; the way the S-boxes are split is random and is altered before each new execution of the block cipher. This makes it very difficult (or even impossible) for an attacker to perform a Differential Power Analysis (DPA) attack by collecting many power traces of the same implementation. Whereas the approach of Sasdrich et al. requires the external computation and communication of new configurations, our approach computes new configurations on the fly with an on-chip configuration generator based on evolutionary algorithms. This reduces the risk of an adversary tampering with the configuration data and takes away the communication delay. Our work is the first to propose the use of EH and Genetic Programming (GP) for this type of countermeasure. More precisely, we explore two methods, Genetic Programming (GP) and Cartesian Genetic Programming (CGP) and we evaluate the feasibility of these methods by measuring the overhead in terms of delay and resource occupation for the block ciphers PRESENT and PRINTcipher. © Springer Nature Switzerland AG 2020.
Journal of Circuits, Systems and Computers (02181266)(14)
Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults. © 2019 World Scientific Publishing Company.
Journal of Circuits, Systems and Computers (02181266)(9)
Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans. © 2018 World Scientific Publishing Company.
Multimedia Tools and Applications (13807501)77(24)pp. 31713-31735
Recently, digital watermarking has become an important technique to preserve patients’ privacy in telemedicine applications. Since, medical information are highly sensitive, security of watermarked medical images becomes a critical issue in telemedicine applications. In this paper, two targeted attacks have been proposed against a key based color image watermarking scheme and also a non-key based one, in order to evaluate their security in telemedicine applications. The target schemes are SVD-based and QR-based color image watermarking algorithms, which their embedding procedures are quit the same. The proposed attacks exploit the prior knowledge of the watermarking algorithms to make changes in the exact embedding spaces. Thus, these changes would cause disruption in extraction procedure. Our experimental results show that the key based watermarking scheme is more secure than the non-key based one. This is because the proposed targeted attack needs to distort the key based watermarked images more than non-key based ones to remove the embedded watermarks. Our proposed targeted attacks also have more efficient performance in removing watermarks than other general attacks such as JPEG compression, Gaussian noise and etc. Finally, these attacks have been proposed to show the vulnerabilities of watermarking schemes in order to help the designers to implement more secure schemes. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.
The Arabian Journal For Science And Engineering (2193567X)(2)
The paper proposes an algorithm for image encryption using the random bit sequence generator and based on chaotic maps. Chaotic Logistic and Tent maps are used to generate required random bit sequences. Pixels of the plain image are permuted using these chaotic functions, and then the image is partitioned into eight bit map planes. In each plane, bits are permuted and substituted according to random bit and random number matrices; these matrices are the products of those functions. The pixels and bit maps permutation stage are based on a chaotic random Ergodic matrix. This chaotic encryption method produces encrypted image whose performance is evaluated using chi-square test, correlation coefficient, number of pixel of change rate (NPCR), unified average changing intensity (UACI), and key space. The histogram of encrypted image is approximated by a uniform distribution with low chi-square factor. Horizontal, vertical, and diagonal correlation coefficients of two adjacent pixels of encrypted image are calculated. These factors are improved compared to other proposed methods. The NPCR and UACI values of encrypted image are also calculated. The result shows that a swift change in the original image will cause a significant change in the ciphered image. Total key space for the proposed method is (2^2, 160), which is large enough to protect the proposed encryption image against any brute-force attack. © 2013 The Author(s).
Telecommunication Systems (15729451)(2)
We proposed an algorithm to encrypt an image in hybrid domain, frequency and time domains. The proposed method is a private key encryption system with two main units, chaotic phase-magnitude transformation unit and chaotic pixel substitution unit. Chaotic phase-magnitude transformation unit works in frequency domain and a 2-D DFT is performed on the plain image to change the domain. A chaotic function, the tent map, is used to generate the pseudo random image, which are combined with the plain image in frequency domain. Chaotic pixel substitution unit works in time domain Bernoulli map is applied to produce another pseudo random image that is mixing with the encrypted image nonlinearly. The performance of the proposed chaotic image encryption system is analysed using a computer simulation. The distribution of histogram of encrypted image is uniform. Chi-square value for encrypted image of our proposed method is considerably low. The MSE of the proposed encrypted image is big enough. The correlation coefficients of the proposed encrypted image in all three directions are sufficiently small. The total key length is large enough to resist the proposed system against any brute-force attack. The proposed scheme is robust against chosen plaintext attacks too. The proposed chaotic image encryption system, which is used frequency and time domain together, is more secure than most of single domain image encryption systems. © 2011 Springer Science+Business Media, LLC.
IETE Journal of Research (03772063)(1)
In this paper, a random bit sequence generator based on chaotic maps is introduced and implemented. In this generator, two chaotic map functions with two different keys are used. The Bifurcation diagram is used to calculate the initial state of the chaotic maps in order to produce the output random bit sequence. Chaotic Logistic and Tent maps classically are defined in an analogue space. In order to implement these chaotic maps on a hardware digital platform, these chaotic maps are modified. Digital chaotic Logistic and Tent maps are introduced. A design for implementation of these modified chaotic maps is also presented. The output bits of two chaotic maps are EX-ORed to produce a random sequence of 1 000 000 bits. These designs are implemented on Field Programmable Gate Array, and the results are reported. The proposed designs are tested by producing 100 samples of 1 000 000 bits, and they pass the standard Federal Information Processing Standard 140-1 and National Institute of Standards and Technology statistical tests for random bit generators. © 2013 by the IETE.
International Journal of Bifurcation and Chaos (02181274)(5)
In this paper, we propose a new one-dimensional, two-segmental nonlinear map by combining tent, triangle and parabola curve functions. We call the proposed map, Mehrab map since its return maps shape is similar to an altar (which we call it "Mehrab"). Definition and properties of Mehrab map along with orbit diagrams, Lyapunov exponents, and its histograms are considered. To generate more uniform density function maps, two modified versions of the proposed Mehrab map are also defined. In the first modification of Mehrab map (FMM), vertical symmetry and transformation to the right are used. Sensitivity to initial condition and total chaotic range of FMM are medium. Probability density function of FMM map is uniform and its histograms show this uniformity. In the second modification of Mehrab (SMM) map, vertical and horizontal symmetry and transformation to the right are used. According to the orbit diagrams and Lyapunov exponents, the sensitivity to initial condition and the total chaotic range of SMM map are large. This property gives more chaotic region to the map. Its histograms prove that the probability density function of SMM is also uniform. © 2012 World Scientific Publishing Company.
Mathematical Problems in Engineering (15635147)
In this paper, we have presented a new permutation-substitution image encryption architecture using chaotic maps and Tompkins-Paige algorithm. The proposed encryption system includes two major parts, chaotic pixels permutation and chaotic pixels substitution. A logistic map is used to generate a bit sequence, which is used to generate pseudorandom numbers in Tompkins-Paige algorithm, in 2D permutation phase. Pixel substitution phase includes two process, the tent pseudorandom image (TPRI) generator and modulo addition operation. All parts of the proposed chaotic encryption system are simulated. Uniformity of the histogram of the proposed encrypted image is justified using the chi-square test, which is less than 2 (255, 0.05). The vertical, horizontal, and diagonal correlation coefficients, as well as their average and RMS values for the proposed encrypted image are calculated that is about 13 less than previous researches. To quantify the difference between the encrypted image and the corresponding plain-image, three measures are used. These are MAE, NPCR, and UACI, which are improved in our proposed system considerably. NPCR of our proposed system is exactly the ideal value of this criterion. The key space of our proposed method is large enough to protect the system against any Brute-force and statistical attacks. © 2009 S. Etemadi Borujeni and M. Eshghi.
Underwater Technology (17560543)
It is required a precise, linear indication of the depth of water in a specific part of the sea. This demands a continuous level measurement. There are a wide variety of ways to produce a signal that tracks the depth of water in a specific part of the sea. Ultrasonic detectors find the distance between seabed to the surface of the water. To measure level, depth, with an ultrasonic range detector, the module is mounted at the bottom of the sea, seabed, looking up the surface. We must measure the time between the transmit pulse and the echo received pulses. Since the ultrasonic signal is traveling at the speed of sound, the time between transmission and echo received is a measure of the distance to the surface,water depth. A micro-controller sends a pulse to the ultrasonic module. The module is transmitting an ultrasonic wave for a short period of time and wait for receiving its echo. As soon as echo received to ultrasonic module, is sent a pulse to micro-controller, which measures the time between two pulses. There are two modes of operation, program mode and run mode. When the unit is powered. it is programmed to start up in the run mode, to detect the distance from the transducer face to a target, depth, in meter. The unit can be placed into program mode at any time by pressing the menu key to alter a value of parameters in order to better suit the application or user preferences. Unit of measurement, type of measurement, set point of alarms and factory setting are some of its parameters. The working time of transition and receiver part of the module is specifies by micro-controller normally for each second 10 ultrasonic pulses are transmitted. The measuring error is approximately 1.25%. Such an error value is acceptable with reception to wavelength of ultrasonic waves. For so many application that the precision of Cm is sufficient ultrasonic level measurement is suitable. The system protected from virtual echoed by using threshold and counting number of echo pulses. © 2002 IEEE.
This report deals with describing permutation of FFT (Fast Fourier Transform) coefficients in speech encryption system. The scrambling algorithm is based on the permutation of the FFT coefficients and provides highly secured scrambled signal by permuting a large number of those coefficients. The algorithm for generation the permutation matrices is explained.This system is useful for a band limited telephone channel and mobile communication. Choice and construction of permutation matrices in scrambling system are considered. Simulation have been done by using C programming language. The results of simulation and tests shows that proposed scrambling achieves extremely high-level security as well as high speech quality. © 2000 IEEE.
This paper describes an encryption system for analog signals based on permutation of samples. The scrambling algorithm is based on the permutation of the samples and provides highly secured scrambled signal by permuting a large number of those samples. The algorithm for generation the permutation matrices is explained. Important items to be considered in designing the system are discussed such as choice and construction of permutation matrices, and configuration of the practical scrambling system. C programming language was used for simulation. The results of simulation and tests shows that proposed scrambling achieve extremely high-level security. The method of choice and generation of permutation matrices, Tompkin-Paig algorithm and maximum length shift register are discussed. Simulations of different parts of the system, include scrambler, descrambler and generation of permutation matrices programs are provided. Miscellaneous methods of objective tests are described. Theoretical and simulation results of these tests are also provided. © 2002 IEEE.
The FFT speech encryption algorithm is tested on speech samples which are recorded using a data acquisition system connected to a PC. The speech samples are read from an input file by the simulation program and the scrambling operation performed on them frame-by-frame. The scrambled speech signal is output through the filter card and the DAC card. The scrambled speech samples are also recorded onto an output file on which the descrambling operations are subsequently performed. The algorithms and results of these simulation tests are provided below. An analog I/O card was used with simulation program. A 12-bit ADC and DAC card was used to capture about 4 seconds of speech at the rate of 8 Ksps. The scrambler and descrambler programs written in C processed the speech file. The main parts of the system are (i) scrambler with permutation and (ii) descrambling with depermutation. Some additional parts such as the ADC, the DAC, the IBC (integer to binary convertor) and the BIC are necessary. The basic functions can, thus be identified as follows: 1) Scrambler includes FFT, permutation and IFFT 2) Descrambler includes FFT, depermutation and IFFT 3) Generation of permutation matrices. © 2002 IEEE.
Scan design is a powerful Design-for-Testability (DFT) technique that enhances controllability and observability of internal nodes of the circuit under test. However, it can increase system vulnerability being a back door to access secret information of a secure chip. In this paper, we present a scan-based design which is robust against scan-based side channel attacks. We use SHA256 secure hash and Blum Blum Shub pseudo random number generator to create a simple challenge/response scheme. The system can be used to enable JTAG instructions for authorized user or control access to IEEE 1687 on-chip instruments. The effectiveness of the proposed method has been verified using NIST statistical test suite. © 2016 IEEE.
