Publication Date: 2025
Computers and Electrical Engineering (00457906)128
This study presents an alternative approach to capacitor switching aimed at lowering switching energy in successive approximation register analog-to-digital converters (SAR ADCs). This approach eliminates energy consumption from the input voltage by establishing a direct connection to the comparator's positive terminal. To mitigate offset drawbacks, a low-power offset-cancellation comparator is employed. Furthermore, by isolating all capacitors connected to the comparator's negative terminal during the switching of reference voltages, the energy overhead introduced by toggling the reference voltages is also ideally reduced to zero. This achieves a theoretical 100% reduction in switching energy compared to conventional SAR ADC methods under idealized assumptions. In practice, non-ideal factors such as parasitic capacitance, charge injection, comparator dynamic power, and control logic overhead contribute to residual energy consumption. This energy reduction is achieved while maintaining a low complexity in the control block. Additionally, this architecture employs only 25% of the capacitors required in traditional design, leading to substantial hardware savings. The suggested 8-bit SAR ADC was simulated in a 65 nm CMOS process with a 1.2 V power supply, 0.9 V reference voltage, and an operating sampling rate of 1 MS/s. As observed in the simulation data, the effective number of bits, power dissipation, and figure of merit are determined to be 6.9 bits, 1.91 µW, and 15.99 fJ/conversion-step, respectively. To evaluate the converter's efficiency, Monte Carlo, corner, and temperature simulations were conducted, demonstrating satisfactory performance. © 2025
